A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE journal of solid-state circuits 2023-01, Vol.58 (1), p.279-290
Hauptverfasser:	Lee, Daewoong, Baek, Jaehyeok, Kwon, Hye-Jung, Kwon, Dae-Hyun, Cho, Chulhee, Kim, Sang-Hoon, An, Donggun, Chang, Chulsoon, Lim, Unhak, Im, Jiyeon, Sung, Wonju, Kim, Hye-Ran, Park, Sun-Young, Kim, Hyoung-Joo, Seol, Hoseok, Kim, Juhwan, Shin, Jungbum, Kang, Gil-Young, Kim, Yong-Hun, Kim, Sooyoung, Park, Wansoo, Kim, Seok-Jung, Lee, Chan-Yong, Lee, Seungseob, Park, Tae-Hoon, Oh, Chi-Sung, Ban, Hyodong, Ko, Hyungjong, Song, Hoyoung, Oh, Tae-Young, Hwang, Sang-Joon, Oh, Kyung-Suk, Choi, Jung-Hwan, Lee, Jooyoung
Format:	Artikel
Sprache:	eng
Schlagworte:	Alternative-data-bus (ADB) Bandwidth Clocks Coils data clock (WCK) Dynamic random access memory Graphics graphics double-data-rate 6 (GDDR6) graphics dynamic random access memory (DRAM) high-speed memory Load modeling merged-multiplexer (MUX) transmitter (TX) Metals quad-skew training Random access memory reference impedance (ZQ) calibration Resistance T-coil wireline transceiver
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2022.3222203