Ring-ExpLWE: A High-Performance and Lightweight Post-Quantum Encryption Scheme for Resource-Constrained IoT Devices

As the Internet of Things (IoT) expands explosively existing network connections, the transmission and processing of private data is facing more serious threats of leakage and theft. Classical public key encryption schemes are difficult to guarantee strong security protection, because the mathematic...

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Veröffentlicht in:IEEE internet of things journal 2022-12, Vol.9 (23), p.24122-24134
Hauptverfasser: Xu, Dongdong, Wang, Xiang, Hao, Yuanchao, Zhang, Zhun, Hao, Qiang, Jia, Haoyu, Dong, Haifeng, Zhang, Longbing
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Sprache:eng
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Zusammenfassung:As the Internet of Things (IoT) expands explosively existing network connections, the transmission and processing of private data is facing more serious threats of leakage and theft. Classical public key encryption schemes are difficult to guarantee strong security protection, because the mathematically hard problems they rely on are no longer difficult to solve under the rapid development of quantum computing. Therefore, a more high-performance and quantum-resistant encryption scheme Ring-ExpLWE is proposed, in which the error vector is sampled in the exponential distribution instead of the binary distribution in the previous Ring-BinLWE. We evaluate the Ring-ExpLWE's security level by analyzing the runtime under quantum hybrid attack and comparing the standard deviation of the noise polynomial coefficients. Compared with Ring-BinLWE, the proposed Ring-ExpLWE requires larger runtime for quantum hybrid attack and has a more discrete noise distribution. Therefore, Ring-ExpLWE can provide a higher security level under the same parameter set. Moreover, the high-performance software and hardware implementations for the Ring-ExpLWE scheme are proposed, respectively. Based on the Cortex-M3 microprocessor platform, encryption, and decryption only require 35.6 and 17.8 ms in our software implementation, respectively. Compared with the previous Ring-BinLWE schemes, while significantly improving the security level, the Area \times Time (AT) of our high-performance and lightweight hardware implementations is reduced by 49.2% and 49.5%, respectively, when the FPGA platform is Spartan 6.
ISSN:2327-4662
2327-4662
DOI:10.1109/JIOT.2022.3189210