A Study on Effects of Deadtime in a Single-phase Multilevel Inverter Using Circuit Topology and the Modulation Method

We quantitatively investigate the reduction of the voltage error caused due to deadtime by introducing multilevel inverters. In particular, the voltage errors of a flying capacitor multilevel inverter with carrier phase shifted modulation, a diode-clamped multilevel inverter with carrier phase disposition modulation, and a 2-level inverter are theoretically investigated via circuit analysis. Based on a theoretical study, the voltage errors of multilevel inverters with different levels, circuit topologies, and modulation methods and the voltage errors of a 2-level inverter, are comparatively verified via simulation and experimental results. Moreover, output current total harmonics distortion (THD) validate based on simulation results. The simulation and experimental results demonstrate that the voltage errors and harmonics are significantly reduced by utilizing the multilevel inverters. We expect that the results presented in this paper will provide useful guidelines for the introduction of multilevel inverters in practical inverter systems.