Low Leakage and High ION/IOFF Ratio in Partial Gated AlGaN/GaN Nanowire Field‐Effect Transistors

Lateral nanowire (NW) field‐effect transistors are fabricated by a top‐down approach on an AlGaN/GaN heterostructure. A combination of dry and anisotropic wet etching is used to form the NW. The channel is controlled by a 2D electric field originating from two partial gates on the parallel sides of...

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Veröffentlicht in:Physica status solidi. PSS-RRL. Rapid research letters 2022-07, Vol.16 (7), p.n/a
Hauptverfasser: Kumar, Akhil S., Ganguly, Swaroop, Saha, Dipankar
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Sprache:eng
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Zusammenfassung:Lateral nanowire (NW) field‐effect transistors are fabricated by a top‐down approach on an AlGaN/GaN heterostructure. A combination of dry and anisotropic wet etching is used to form the NW. The channel is controlled by a 2D electric field originating from two partial gates on the parallel sides of the nanowire channel. While a larger overlap of the gate with the channel region, as in a gate‐all‐around transistor, improves gate control in terms of transconductance gm, gate leakage current and ION/IOFF deteriorate. Partial overlapping gate transistors are found to provide a trade‐off, providing extremely low gate leakage current (≈10 μA cm−2), very low IOFF (100 fA μm−1), and very high ION/IOFF (5 × 108). Despite the nature of the partial gate, a good subthreshold swing (SS) of ≈79 mV decade−1 is observed. Various transistor performance parameters can be tuned within a certain window of trade‐offs between them as the transistor evolves from a partial gate to a gate‐all‐around structure. A 1D nature of the channel near the transistor threshold voltage is found to offset the limitations of the partial gate. A high‐performance dual‐gate nanowire field‐effect‐transistor by a partial gated channel region with exceptionally low gate leakage, high ON/OFF ratio, and small sub‐threshold leakage current is demonstrated. The channel leakage is controlled by the potential from both gates. The device properties can be tuned by controlling the overlapping area between the gate and channel region.
ISSN:1862-6254
1862-6270
DOI:10.1002/pssr.202200100