Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length
A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic lay...
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| Veröffentlicht in: | IEEE electron device letters 2022-08, Vol.43 (8), p.1183-1186 |
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| creator | Xiao, Z. R. Wang, Q. Zhu, H. L. Chen, Z. Zhang, Y. K. Li, J. J. Zhou, N. Gao, J. F. Ai, X. Z. Lu, S. S. Huang, W. X. Xiong, W. J. Kong, Z. Z. Xiang, J. J. Zhang, Y. Zhao, J. Liu, J. B. Lu, Y. H. Bai, G. B. He, X. B. Du, A. Y. Wu, Z. H. Yang, T. Li, J. F. Luo, J. Wang, W. W. Ye, T. C. |
| description | A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large \text{I}_{\text {on}}/\text {I}_{\text {off}} ratio of {6.28}\times {10}^{{9}} were achieved. The device performance and it's optimization were also investigated with the reduction of the external resistance and numerical simulations. |
| doi_str_mv | 10.1109/LED.2022.3187006 |
| format | Article |
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R. ; Wang, Q. ; Zhu, H. L. ; Chen, Z. ; Zhang, Y. K. ; Li, J. J. ; Zhou, N. ; Gao, J. F. ; Ai, X. Z. ; Lu, S. S. ; Huang, W. X. ; Xiong, W. J. ; Kong, Z. Z. ; Xiang, J. J. ; Zhang, Y. ; Zhao, J. ; Liu, J. B. ; Lu, Y. H. ; Bai, G. B. ; He, X. B. ; Du, A. Y. ; Wu, Z. H. ; Yang, T. ; Li, J. F. ; Luo, J. ; Wang, W. W. ; Ye, T. C.</creator><creatorcontrib>Xiao, Z. R. ; Wang, Q. ; Zhu, H. L. ; Chen, Z. ; Zhang, Y. K. ; Li, J. J. ; Zhou, N. ; Gao, J. F. ; Ai, X. Z. ; Lu, S. S. ; Huang, W. X. ; Xiong, W. J. ; Kong, Z. Z. ; Xiang, J. J. ; Zhang, Y. ; Zhao, J. ; Liu, J. B. ; Lu, Y. H. ; Bai, G. B. ; He, X. B. ; Du, A. Y. ; Wu, Z. H. ; Yang, T. ; Li, J. F. ; Luo, J. ; Wang, W. W. ; Ye, T. C.</creatorcontrib><description><![CDATA[A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large <inline-formula> <tex-math notation="LaTeX">\text{I}_{\text {on}}/\text {I}_{\text {off}} </tex-math></inline-formula> ratio of <inline-formula> <tex-math notation="LaTeX">{6.28}\times {10}^{{9}} </tex-math></inline-formula> were achieved. The device performance and it's optimization were also investigated with the reduction of the external resistance and numerical simulations.]]></description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2022.3187006</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>3D monolithic integration ; Epitaxial growth ; Etching ; Field effect transistors ; Ion/Ioff ratio ; Logic gates ; nanosheet ; Nanosheets ; Optimization ; Process control ; Self alignment ; Semiconductor devices ; Silicon ; Silicon germanium ; Thickness ; VCNFET ; Vertical C-shaped-channel nanosheet FET</subject><ispartof>IEEE electron device letters, 2022-08, Vol.43 (8), p.1183-1186</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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R.</creatorcontrib><creatorcontrib>Wang, Q.</creatorcontrib><creatorcontrib>Zhu, H. L.</creatorcontrib><creatorcontrib>Chen, Z.</creatorcontrib><creatorcontrib>Zhang, Y. K.</creatorcontrib><creatorcontrib>Li, J. J.</creatorcontrib><creatorcontrib>Zhou, N.</creatorcontrib><creatorcontrib>Gao, J. F.</creatorcontrib><creatorcontrib>Ai, X. Z.</creatorcontrib><creatorcontrib>Lu, S. S.</creatorcontrib><creatorcontrib>Huang, W. X.</creatorcontrib><creatorcontrib>Xiong, W. J.</creatorcontrib><creatorcontrib>Kong, Z. Z.</creatorcontrib><creatorcontrib>Xiang, J. J.</creatorcontrib><creatorcontrib>Zhang, Y.</creatorcontrib><creatorcontrib>Zhao, J.</creatorcontrib><creatorcontrib>Liu, J. B.</creatorcontrib><creatorcontrib>Lu, Y. H.</creatorcontrib><creatorcontrib>Bai, G. B.</creatorcontrib><creatorcontrib>He, X. B.</creatorcontrib><creatorcontrib>Du, A. Y.</creatorcontrib><creatorcontrib>Wu, Z. H.</creatorcontrib><creatorcontrib>Yang, T.</creatorcontrib><creatorcontrib>Li, J. F.</creatorcontrib><creatorcontrib>Luo, J.</creatorcontrib><creatorcontrib>Wang, W. W.</creatorcontrib><creatorcontrib>Ye, T. C.</creatorcontrib><title>Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description><![CDATA[A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large <inline-formula> <tex-math notation="LaTeX">\text{I}_{\text {on}}/\text {I}_{\text {off}} </tex-math></inline-formula> ratio of <inline-formula> <tex-math notation="LaTeX">{6.28}\times {10}^{{9}} </tex-math></inline-formula> were achieved. The device performance and it's optimization were also investigated with the reduction of the external resistance and numerical simulations.]]></description><subject>3D monolithic integration</subject><subject>Epitaxial growth</subject><subject>Etching</subject><subject>Field effect transistors</subject><subject>Ion/Ioff ratio</subject><subject>Logic gates</subject><subject>nanosheet</subject><subject>Nanosheets</subject><subject>Optimization</subject><subject>Process control</subject><subject>Self alignment</subject><subject>Semiconductor devices</subject><subject>Silicon</subject><subject>Silicon germanium</subject><subject>Thickness</subject><subject>VCNFET</subject><subject>Vertical C-shaped-channel nanosheet FET</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM9LwzAYhoMoOKd3wUvAc2Z-tulR6zaFooJTjyFrv9rOmtYkO_jf27Hh6YOX530_eBC6ZHTGGM1uivn9jFPOZ4LplNLkCE2YUppQlYhjNKGpZEQwmpyisxA2lDIpUzlBwzv42Ja2wzl5bewAFckb6xx0-Mm6PjQAES_mq4AXYOPWQ4U_2tjgFw9lGwDnvYu-73Bf47t-zA9lsmra8stBCNi6Ci9tBFKA-4zNOTqpbRfg4nCn6G2czx9I8bx8zG8LUvKMRVLWma5rbbmSHMoqU4xaK5VWSqUVSGCJ0qJKlaBWy6xWXCeQJtKuS24zthZiiq73u4Pvf7YQotn0W-_Gl4Yn45wSIqEjRfdU6fsQPNRm8O239b-GUbPzakavZufVHLyOlat9pQWAfzzTjI6E-AORKXKc</recordid><startdate>20220801</startdate><enddate>20220801</enddate><creator>Xiao, Z. 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W.</creatorcontrib><creatorcontrib>Ye, T. C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xiao, Z. R.</au><au>Wang, Q.</au><au>Zhu, H. L.</au><au>Chen, Z.</au><au>Zhang, Y. K.</au><au>Li, J. J.</au><au>Zhou, N.</au><au>Gao, J. F.</au><au>Ai, X. Z.</au><au>Lu, S. S.</au><au>Huang, W. X.</au><au>Xiong, W. J.</au><au>Kong, Z. Z.</au><au>Xiang, J. J.</au><au>Zhang, Y.</au><au>Zhao, J.</au><au>Liu, J. B.</au><au>Lu, Y. H.</au><au>Bai, G. B.</au><au>He, X. B.</au><au>Du, A. Y.</au><au>Wu, Z. H.</au><au>Yang, T.</au><au>Li, J. F.</au><au>Luo, J.</au><au>Wang, W. W.</au><au>Ye, T. C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2022-08-01</date><risdate>2022</risdate><volume>43</volume><issue>8</issue><spage>1183</spage><epage>1186</epage><pages>1183-1186</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract><![CDATA[A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large <inline-formula> <tex-math notation="LaTeX">\text{I}_{\text {on}}/\text {I}_{\text {off}} </tex-math></inline-formula> ratio of <inline-formula> <tex-math notation="LaTeX">{6.28}\times {10}^{{9}} </tex-math></inline-formula> were achieved. The device performance and it's optimization were also investigated with the reduction of the external resistance and numerical simulations.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LED.2022.3187006</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0003-0840-2963</orcidid><orcidid>https://orcid.org/0000-0001-9728-5994</orcidid><orcidid>https://orcid.org/0000-0002-2384-9037</orcidid><orcidid>https://orcid.org/0000-0002-3746-404X</orcidid><orcidid>https://orcid.org/0000-0002-1594-5969</orcidid><orcidid>https://orcid.org/0000-0003-1627-8915</orcidid><orcidid>https://orcid.org/0000-0003-4552-883X</orcidid><orcidid>https://orcid.org/0000-0002-0045-1288</orcidid><orcidid>https://orcid.org/0000-0002-5122-6806</orcidid></addata></record> |
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| subjects | 3D monolithic integration Epitaxial growth Etching Field effect transistors Ion/Ioff ratio Logic gates nanosheet Nanosheets Optimization Process control Self alignment Semiconductor devices Silicon Silicon germanium Thickness VCNFET Vertical C-shaped-channel nanosheet FET |
| title | Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length |
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