Low temperature epitaxy of tensile-strained Si:P

•550 °C epitaxy of tensile SiP. with disilane and phosphine.•Various strategies evaluated to obtain low resistivities and high [P]subst.•High phosphine to disilane mass-flow, low H2 carrier flow and high pressure.•Smooth and uniform t-Si:P layers with a substitutional P concentration of 6.3%.•Electrical resistivity much lower than with a chlorinated chemistry. Our long-term aim was to explore the Low Temperature Cyclic Deposition/Etch (CDE) of tensile-Si:P, in order to engineer the Sources and Drains of n-type Field Effect Transistors. We wanted to have high amounts of tensile strain and low resistivities in tensile Si:P layers grown at 550 °C, with (i) mainstream Si2H6 + PH3 gases for the non-selective deposition of t-Si:P and (ii) HCl + GeH4 for the selective etches of amorphous-Si:P versus monocrystalline Si:P (to have selectivity on patterned wafers). In the current study, we have focused on the deposition in such processes, having shown beforehand that, indeed, t-Si:P could be etched at 550 °C with HCl + GeH4 if the process conditions were right (Hartmann J.M. and Veillerot M., 2020 Semicond. Sci. Technol. 35 015015). Thanks to (i) high F(PH3)/(2*F(Si2H6)) Mass-Flow Ratios (MFR), (ii) a reduction of the H2 carrier flow, from the reference value of a few tens of standard liters per minute down to 1/5th of it and (iii) a chamber pressure increase, from 20 Torr up to 90 Torr, we succeeded in dramatically increasing the “substitutional” P concentration. and reaching values as high as 7.9%. 40 Torr was the best pressure in order to simultaneously have (i) a high “substitutional” P concentration (6.3%), (ii) a reasonable t-Si:P growth rate (5.5 nm min−1) and (iii) a low electrical resistivity (0.41 mOhm·cm), without being hampered by a layer uniformity that would be too degraded to be of use in actual devices. Those t-Si:P layers, grown with a MFR of 0.46, were of superior crystalline quality (in X-Ray Diffraction) and smooth (from haze measurements).