Performance analysis of a novel 8T SRAM cell

This paper tends to design of a, new 8T CMOS SRAM cell to improve the stability and to decrease dynamic power. To meet the current requirements of the electronic industry we compared our results with the existing data. N-curve metrics has been used to investigate the stability of proposed 8T SRAM cell. Usage of a single bit line (charging/discharging) during the write operation in the proposed 8T SRAM leads to the great reduction in dynamic power consumption.