Enabling efficient sub-block disabled caches using coarse grain spatial predictions

Reducing the supply voltage in today′s process technologies introduces significant reliability challenges for on-chip SRAM arrays. As a reaction, many Cache Fault-Tolerance (CFT) techniques have been developed to ensure error free and performance efficient execution in the presence of faults. A class of recent CFT techniques are based on the concept of disabling cache portions, such as (sub-)blocks or words that include defective bits, and reconfiguring operational ones (e.g., physical or logical neighbor (sub-)blocks). All those techniques require significant circuit modifications which may pose unacceptable overheads to time-sensitive L1 caches. In this work we propose to deal with the cache reliability problem at a very different level. We assume that faulty caches are enhanced with the ability of disabling their defective parts at different sub-block granularities. The key idea is to leverage the spatial reuse patterns of the memory blocks (not all the data fetched into the cache is accessed) in order to mask out the additional, due-to-faults, cache misses. To this end, we propose a new class of frugal spatial predictors (with 24-bytes storage requirements) to orchestrate the replacement decisions of the fully and partially functional cache blocks. Our evaluation results reveal that the proposed approach is able to offer 32.3% on average, among all studied percentage of failures, increase in hit ratio in first level data caches (64.6% in instruction caches) over a conventional faulty cache (based on block disabling). Further, experimental results reveal the superiority of the proposed method with respect to Instructions-Per-Cycle and Energy-Delay-Product.