A Novel architecture for low-jitter multi-GHz frequency synthesis

A phase-locked loop (PLL) cascade driven by a crystal oscillator and a free running dielectric resonator oscillator (DRO) is proposed. For minimizing phase noise, spurious tones and jitter, a programmable PLL1 in the lower GHz range is used to drive a millimeter-wave (mmW) PLL2 with a fixed frequency multiplication factor. The phase noise analysis results in two optimum bandwidths of the two PLLs for the lowest output jitter of the cascade. Phase noise and spurious tones (spurs) in PLL1 are further reduced by dividing the output frequency of PLL1 and up-converting it by means of a single-sideband (SSB) mixer driven by the DRO. By including the SSB mixer in the feedback loop of PLL1 manual tuning of the DRO is avoided, and a low-noise free running DRO can be employed. An exemplary design in SiGe BiCMOS technology is presented.