A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction

This paper presents an injection-locked clock multiplier (ILCM) with a digital self-alignment frequency tracking loop (SA-FTL) to reduce the reference spur by calibrating the frequency mismatch and delay offset. To improve the power efficiency, the SA-FTL detects errors in low frequency, where the high-frequency edges from the oscillator are captured by a double-edge snapshot block. The proposed ILCM is fabricated in a 65 nm CMOS process. It has an active area of 0.045 mm2 and consumes 3.1 mW power at 2.5 GHz output. The measured reference spur is -55.6 dB, showing a 15.9 dB improvement with the proposed SA-FTL. •An injection-locked clock multiplier (ILCM) achieves low reference spur.•The mechanism of the reference spur in the ILCM with the conventional FTL.•Capturing high-frequency edges with a double-edge snapshot block saves power.•Errors are calibrated by a digital self-alignment frequency tracking loop (SA-FTL).•The calibration runs at different phases to decouple the error sources.