An Efficient FIR Filter Based on Hardware Sharing Architecture Using CSD Coefficient Grouping for Wireless Application

FIR filter is an essential part of digital signal processing that is extensively used in many areas such as wireless applications and digital processing system. The FIR filter design is inherently stable and has a linear phase characteristic under symmetric conditions, but its implementation often involves complexity and a large filter length to achieve specific design requirements. In this paper, the complexity of the FIR filter is reduced by eliminating the repeated subexpression in a canonic signed digit (CSD) number system based filter operation. A new grouping method has been proposed for the CSD number system-based filter coefficient to minimize the number of unpaired nonzero bits in the filter coefficient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11 % as compared to other existing schemes. Further, an efficient FIR filter with hardware sharing architecture is designed and implemented to achieve a 14.65 % reduction in average power consumption, and the average operation speed is increased by 10.1 % compared to the other existing filter structures.