Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator
Significant innovation has been made in the development of public-key cryptography that is able to withstand quantum attacks, known as post-quantum cryptography (PQC). This paper focuses on the development of an efficient PQC hardware implementation. Specifically, an implementation of the binary Rin...
Gespeichert in:
| Veröffentlicht in: | IEEE computer architecture letters 2022-01, Vol.21 (1), p.17-20 |
|---|---|
| Hauptverfasser: | , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 20 |
|---|---|
| container_issue | 1 |
| container_start_page | 17 |
| container_title | IEEE computer architecture letters |
| container_volume | 21 |
| creator | Lucas, Benjamin J. Alwan, Ali Murzello, Marion Tu, Yazheng He, Pengzhou Schwartz, Andrew J. Guevara, David Guin, Ujjwal Juretus, Kyle Xie, Jiafeng |
| description | Significant innovation has been made in the development of public-key cryptography that is able to withstand quantum attacks, known as post-quantum cryptography (PQC). This paper focuses on the development of an efficient PQC hardware implementation. Specifically, an implementation of the binary Ring-learning-with-errors (BRLWE)-based encryption scheme, a promising lightweight PQC suitable for resource-constrained applications, is proposed. The paper first develops the mathematical formulation to present the proposed algorithmic process. The corresponding hardware accelerators are then described in detail. Finally, comparisons with previous implementations are provided to demonstrate the superior performance of the proposed design. For instance, the proposed low-complexity accelerator has 34.7% less area-delay product (ADP) than the state-of-the-art design for n=256 n=256 in the field-programmable gate array (FPGA) platform. Apart from the efficiency of the hardware architectures, the proposed design also has a complete input/output processing setup, and thus is feasible for emerging lightweight applications. |
| doi_str_mv | 10.1109/LCA.2022.3160394 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2645253548</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9737700</ieee_id><sourcerecordid>2645253548</sourcerecordid><originalsourceid>FETCH-LOGICAL-c333t-d850572ffaf4667cfced77e169511b853f023603fa8b64aaa64ff12e494fbac13</originalsourceid><addsrcrecordid>eNo9kM1Lw0AQxRdRsFbvgpcFz6mz38mxhtYWAn6geFy229ma0iR1k1L8701p6WXeHN6befwIuWcwYgyypyIfjzhwPhJMg8jkBRkwpXSiQcvL8670Nblp2zWA1CKVAzItytVPt8fDpDMXl3sXkc6r7QYrrDvXlU1Nm0Cfy9rFP_pR1quk-J7Qt_ecjr3HDUbXNfGWXAW3afHupEPyNZ185rOkeH2Z5-Mi8UKILlmmCpThIbggtTY-eFwag0xnirFFqkQALvr6waULLZ1zWobAOMpMhoXzTAzJ4_HuNja_O2w7u252se5fWq6l4koomfYuOLp8bNo2YrDbWFZ9f8vAHmjZnpY90LInWn3k4RgpEfFsz4wwBkD8A_DPZJ0</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2645253548</pqid></control><display><type>article</type><title>Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator</title><source>IEEE Electronic Library (IEL)</source><creator>Lucas, Benjamin J. ; Alwan, Ali ; Murzello, Marion ; Tu, Yazheng ; He, Pengzhou ; Schwartz, Andrew J. ; Guevara, David ; Guin, Ujjwal ; Juretus, Kyle ; Xie, Jiafeng</creator><creatorcontrib>Lucas, Benjamin J. ; Alwan, Ali ; Murzello, Marion ; Tu, Yazheng ; He, Pengzhou ; Schwartz, Andrew J. ; Guevara, David ; Guin, Ujjwal ; Juretus, Kyle ; Xie, Jiafeng</creatorcontrib><description><![CDATA[Significant innovation has been made in the development of public-key cryptography that is able to withstand quantum attacks, known as post-quantum cryptography (PQC). This paper focuses on the development of an efficient PQC hardware implementation. Specifically, an implementation of the binary Ring-learning-with-errors (BRLWE)-based encryption scheme, a promising lightweight PQC suitable for resource-constrained applications, is proposed. The paper first develops the mathematical formulation to present the proposed algorithmic process. The corresponding hardware accelerators are then described in detail. Finally, comparisons with previous implementations are provided to demonstrate the superior performance of the proposed design. For instance, the proposed low-complexity accelerator has 34.7% less area-delay product (ADP) than the state-of-the-art design for <inline-formula><tex-math notation="LaTeX">n=256</tex-math> <mml:math><mml:mrow><mml:mi>n</mml:mi><mml:mo>=</mml:mo><mml:mn>256</mml:mn></mml:mrow></mml:math><inline-graphic xlink:href="xie-ieq1-3160394.gif"/> </inline-formula> in the field-programmable gate array (FPGA) platform. Apart from the efficiency of the hardware architectures, the proposed design also has a complete input/output processing setup, and thus is feasible for emerging lightweight applications.]]></description><identifier>ISSN: 1556-6056</identifier><identifier>EISSN: 1556-6064</identifier><identifier>DOI: 10.1109/LCA.2022.3160394</identifier><identifier>CODEN: ICALC3</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Arithmetic ; Binary Ring-LWE ; complete processing setup ; Computer architecture ; Computers ; Cryptography ; Encryption ; Field programmable gate arrays ; Hardware ; Hardware acceleration ; hardware design ; Lightweight ; lightweight post-quantum cryptography ; Quantum cryptography ; Registers</subject><ispartof>IEEE computer architecture letters, 2022-01, Vol.21 (1), p.17-20</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c333t-d850572ffaf4667cfced77e169511b853f023603fa8b64aaa64ff12e494fbac13</citedby><cites>FETCH-LOGICAL-c333t-d850572ffaf4667cfced77e169511b853f023603fa8b64aaa64ff12e494fbac13</cites><orcidid>0000-0002-4814-1318 ; 0000-0001-5946-4844 ; 0000-0001-6588-4167 ; 0000-0002-4819-8728 ; 0000-0003-3461-4548</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9737700$$EHTML$$P50$$Gieee$$Hfree_for_read</linktohtml><link.rule.ids>314,780,784,796,27922,27923,54756</link.rule.ids></links><search><creatorcontrib>Lucas, Benjamin J.</creatorcontrib><creatorcontrib>Alwan, Ali</creatorcontrib><creatorcontrib>Murzello, Marion</creatorcontrib><creatorcontrib>Tu, Yazheng</creatorcontrib><creatorcontrib>He, Pengzhou</creatorcontrib><creatorcontrib>Schwartz, Andrew J.</creatorcontrib><creatorcontrib>Guevara, David</creatorcontrib><creatorcontrib>Guin, Ujjwal</creatorcontrib><creatorcontrib>Juretus, Kyle</creatorcontrib><creatorcontrib>Xie, Jiafeng</creatorcontrib><title>Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator</title><title>IEEE computer architecture letters</title><addtitle>LCA</addtitle><description><![CDATA[Significant innovation has been made in the development of public-key cryptography that is able to withstand quantum attacks, known as post-quantum cryptography (PQC). This paper focuses on the development of an efficient PQC hardware implementation. Specifically, an implementation of the binary Ring-learning-with-errors (BRLWE)-based encryption scheme, a promising lightweight PQC suitable for resource-constrained applications, is proposed. The paper first develops the mathematical formulation to present the proposed algorithmic process. The corresponding hardware accelerators are then described in detail. Finally, comparisons with previous implementations are provided to demonstrate the superior performance of the proposed design. For instance, the proposed low-complexity accelerator has 34.7% less area-delay product (ADP) than the state-of-the-art design for <inline-formula><tex-math notation="LaTeX">n=256</tex-math> <mml:math><mml:mrow><mml:mi>n</mml:mi><mml:mo>=</mml:mo><mml:mn>256</mml:mn></mml:mrow></mml:math><inline-graphic xlink:href="xie-ieq1-3160394.gif"/> </inline-formula> in the field-programmable gate array (FPGA) platform. Apart from the efficiency of the hardware architectures, the proposed design also has a complete input/output processing setup, and thus is feasible for emerging lightweight applications.]]></description><subject>Arithmetic</subject><subject>Binary Ring-LWE</subject><subject>complete processing setup</subject><subject>Computer architecture</subject><subject>Computers</subject><subject>Cryptography</subject><subject>Encryption</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Hardware acceleration</subject><subject>hardware design</subject><subject>Lightweight</subject><subject>lightweight post-quantum cryptography</subject><subject>Quantum cryptography</subject><subject>Registers</subject><issn>1556-6056</issn><issn>1556-6064</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><recordid>eNo9kM1Lw0AQxRdRsFbvgpcFz6mz38mxhtYWAn6geFy229ma0iR1k1L8701p6WXeHN6befwIuWcwYgyypyIfjzhwPhJMg8jkBRkwpXSiQcvL8670Nblp2zWA1CKVAzItytVPt8fDpDMXl3sXkc6r7QYrrDvXlU1Nm0Cfy9rFP_pR1quk-J7Qt_ecjr3HDUbXNfGWXAW3afHupEPyNZ185rOkeH2Z5-Mi8UKILlmmCpThIbggtTY-eFwag0xnirFFqkQALvr6waULLZ1zWobAOMpMhoXzTAzJ4_HuNja_O2w7u252se5fWq6l4koomfYuOLp8bNo2YrDbWFZ9f8vAHmjZnpY90LInWn3k4RgpEfFsz4wwBkD8A_DPZJ0</recordid><startdate>202201</startdate><enddate>202201</enddate><creator>Lucas, Benjamin J.</creator><creator>Alwan, Ali</creator><creator>Murzello, Marion</creator><creator>Tu, Yazheng</creator><creator>He, Pengzhou</creator><creator>Schwartz, Andrew J.</creator><creator>Guevara, David</creator><creator>Guin, Ujjwal</creator><creator>Juretus, Kyle</creator><creator>Xie, Jiafeng</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>ESBDL</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><orcidid>https://orcid.org/0000-0002-4814-1318</orcidid><orcidid>https://orcid.org/0000-0001-5946-4844</orcidid><orcidid>https://orcid.org/0000-0001-6588-4167</orcidid><orcidid>https://orcid.org/0000-0002-4819-8728</orcidid><orcidid>https://orcid.org/0000-0003-3461-4548</orcidid></search><sort><creationdate>202201</creationdate><title>Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator</title><author>Lucas, Benjamin J. ; Alwan, Ali ; Murzello, Marion ; Tu, Yazheng ; He, Pengzhou ; Schwartz, Andrew J. ; Guevara, David ; Guin, Ujjwal ; Juretus, Kyle ; Xie, Jiafeng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c333t-d850572ffaf4667cfced77e169511b853f023603fa8b64aaa64ff12e494fbac13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Arithmetic</topic><topic>Binary Ring-LWE</topic><topic>complete processing setup</topic><topic>Computer architecture</topic><topic>Computers</topic><topic>Cryptography</topic><topic>Encryption</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Hardware acceleration</topic><topic>hardware design</topic><topic>Lightweight</topic><topic>lightweight post-quantum cryptography</topic><topic>Quantum cryptography</topic><topic>Registers</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lucas, Benjamin J.</creatorcontrib><creatorcontrib>Alwan, Ali</creatorcontrib><creatorcontrib>Murzello, Marion</creatorcontrib><creatorcontrib>Tu, Yazheng</creatorcontrib><creatorcontrib>He, Pengzhou</creatorcontrib><creatorcontrib>Schwartz, Andrew J.</creatorcontrib><creatorcontrib>Guevara, David</creatorcontrib><creatorcontrib>Guin, Ujjwal</creatorcontrib><creatorcontrib>Juretus, Kyle</creatorcontrib><creatorcontrib>Xie, Jiafeng</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE Open Access Journals</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE computer architecture letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Lucas, Benjamin J.</au><au>Alwan, Ali</au><au>Murzello, Marion</au><au>Tu, Yazheng</au><au>He, Pengzhou</au><au>Schwartz, Andrew J.</au><au>Guevara, David</au><au>Guin, Ujjwal</au><au>Juretus, Kyle</au><au>Xie, Jiafeng</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator</atitle><jtitle>IEEE computer architecture letters</jtitle><stitle>LCA</stitle><date>2022-01</date><risdate>2022</risdate><volume>21</volume><issue>1</issue><spage>17</spage><epage>20</epage><pages>17-20</pages><issn>1556-6056</issn><eissn>1556-6064</eissn><coden>ICALC3</coden><abstract><![CDATA[Significant innovation has been made in the development of public-key cryptography that is able to withstand quantum attacks, known as post-quantum cryptography (PQC). This paper focuses on the development of an efficient PQC hardware implementation. Specifically, an implementation of the binary Ring-learning-with-errors (BRLWE)-based encryption scheme, a promising lightweight PQC suitable for resource-constrained applications, is proposed. The paper first develops the mathematical formulation to present the proposed algorithmic process. The corresponding hardware accelerators are then described in detail. Finally, comparisons with previous implementations are provided to demonstrate the superior performance of the proposed design. For instance, the proposed low-complexity accelerator has 34.7% less area-delay product (ADP) than the state-of-the-art design for <inline-formula><tex-math notation="LaTeX">n=256</tex-math> <mml:math><mml:mrow><mml:mi>n</mml:mi><mml:mo>=</mml:mo><mml:mn>256</mml:mn></mml:mrow></mml:math><inline-graphic xlink:href="xie-ieq1-3160394.gif"/> </inline-formula> in the field-programmable gate array (FPGA) platform. Apart from the efficiency of the hardware architectures, the proposed design also has a complete input/output processing setup, and thus is feasible for emerging lightweight applications.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LCA.2022.3160394</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-4814-1318</orcidid><orcidid>https://orcid.org/0000-0001-5946-4844</orcidid><orcidid>https://orcid.org/0000-0001-6588-4167</orcidid><orcidid>https://orcid.org/0000-0002-4819-8728</orcidid><orcidid>https://orcid.org/0000-0003-3461-4548</orcidid><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 1556-6056 |
| ispartof | IEEE computer architecture letters, 2022-01, Vol.21 (1), p.17-20 |
| issn | 1556-6056 1556-6064 |
| language | eng |
| recordid | cdi_proquest_journals_2645253548 |
| source | IEEE Electronic Library (IEL) |
| subjects | Arithmetic Binary Ring-LWE complete processing setup Computer architecture Computers Cryptography Encryption Field programmable gate arrays Hardware Hardware acceleration hardware design Lightweight lightweight post-quantum cryptography Quantum cryptography Registers |
| title | Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T09%3A27%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Lightweight%20Hardware%20Implementation%20of%20Binary%20Ring-LWE%20PQC%20Accelerator&rft.jtitle=IEEE%20computer%20architecture%20letters&rft.au=Lucas,%20Benjamin%20J.&rft.date=2022-01&rft.volume=21&rft.issue=1&rft.spage=17&rft.epage=20&rft.pages=17-20&rft.issn=1556-6056&rft.eissn=1556-6064&rft.coden=ICALC3&rft_id=info:doi/10.1109/LCA.2022.3160394&rft_dat=%3Cproquest_cross%3E2645253548%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2645253548&rft_id=info:pmid/&rft_ieee_id=9737700&rfr_iscdi=true |