Masking Noise Pulses When Collecting a Charge from the Tracks of Single Ionizing Particles in a Majority Element Based on CMOS NAND Logic

The results of modeling the processes of masking noise arising from the collection of charge by transistors from the tracks of single ionizing particles with a linear energy transfer (LET) of 60 MeV cm 2 /mg are presented in a majority element based on the NAND CMOS logic. They were modeled using the 3D TCAD physical models of CMOS transistors according to the design standard of 65 nm bulk technology with the shallow trench isolation of transistor groups. Charge collection from the track leads to the formation of noise pulses. The majority element has an original topological structure, in which the transistors of the output gate 3NAND are inserted one-by-one into the corresponding transistor groups of the two-input 2NAND elements. A feature of the majority element is masking the noise (blocking their transmission to the output) that occurs when the charge is collected from the track after switching the element at the inputs from 0 to 1 and before switching the element at the inputs from 1 to 0. When masking, no noise pulses appear at the output of the majority element.