A translinear principle based low-power high-precision RMS-to-DC converter in CMOS technology

In the present study, a low-power high-precision current-mode CMOS true root mean square (RMS)-to-DC converter is presented based on the translinear (TL) loop principle. The use of TL is considered the best choice for designing RMS-to-DC converters in the saturation region. The proposed converter is based on a mathematical technique, and its circuit structure includes absolute-value, averaging, squarer, and square root circuits. The main advantages of the proposed converter are low power consumption and high bandwidth as a result of the new design of the circuits that operate in the saturation region. Furthermore, to implement the squarer circuit, we use the TL principle with a special arrangement of transistors. In the design of this block, two TLs use one bias branch instead of two branches. The use of a common bias branch leads to low power dissipation in this circuit. The proposed converter consumes 61.4 μW and requires a low supply voltage of 1.8 V over an input range of 40 μA to 1 mA. The Monte Carlo analyses of transistor parameters, such as threshold voltage and aspect ratio, demonstrate the stable performance of the circuits. The circuit is designed in Cadence and the post-layout simulation is performed in HSPICE using TSMC level 49 parameters ( BSIM3v3 ) in 0.18 μm technology. The simulation results demonstrate a linearity error of 2%, a maximum power consumption of 61.4 μW, and a high 3-dB bandwidth.