A new low-power Dynamic-GDI full adder in CNFET technology

In this paper, a new low-power full-adder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the proposed approach, the basic logic circuits such as XOR and XNOR gates are implemented which results in a full-swing, full-adder cell in the CNFET technology. The proposed circuit is simulated in HSPICE using CNFET model parameters. Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder circuit. •A new Dynamic-GDI Low-Power Full-Adder circuit in CNFET technology is presented.•The design is based on the proper combination of Dynamic and GDI logic design techniques.•The proposed design not only significantly reduces the power consumption, but also reduces the PDP and layout area considerably.•The performance of the proposed circuit is simulated in HSPICE, using the STANFORD CNFET model parameters.