Interface Algorithm Design for Power Hardware-in-the-loop Emulation of Modular Multilevel Converter Within High-Voltage Direct Current Systems

Power hardware-in-the-loop (PHIL) simulation combines the advantages of digital simulation and physical experiment, which provides great convenience for research and verification of a complex electric system, such as the high-voltage direct current (HVdc) system. The digital interface algorithm realizes interconnection of the digital and physical system, but it is also the main factor to affect stability and accuracy of the PHIL results. In this article, the damping impedance interface algorithm is adopted to test the performance of a modular multilevel converter (MMC) connected into an HVdc system. Instead of online acquiring the exact MMC dc impedance, a simple RLC damping impedance is proposed to ensure stability and particularly, low-frequency accuracy for the PHIL system. Moreover, as testing in the laboratory does not allow hundreds of MVA-rated physical MMC, suitable scaling factors are proposed to design a scaled-down MMC prototype which presents identical dynamic characteristic with a full-scale MMC. A PHIL setup including RT-LAB real-time simulator, power amplifier, and a scaled-down MMC prototype is built and the experiments confirm the effectiveness of the proposed interface algorithm.