Adapting M2 silicon half-wafers processing on industrial-scale equipment dedicated to 4″ solar technology

Purpose The purpose of this study is to address the issue of technology equipment formerly dedicated to the process of 4- and even 5-inch photovoltaic cells and whose use has become critical with the evolution of silicon wafer size standards (M2–M10). Fortunately, the recent concept of 6''...

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Veröffentlicht in:Microelectronics international 2021-08, Vol.38 (2), p.55-59
Hauptverfasser: Boumaour, Messaoud, Kermadi, Salim, Sali, Samira, El-Amrani, Abdelkader, Mezghiche, Salah, Zougar, Lyes, Boulahdjel, Sarah, Pellegrin, Yvon
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Sprache:eng
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Zusammenfassung:Purpose The purpose of this study is to address the issue of technology equipment formerly dedicated to the process of 4- and even 5-inch photovoltaic cells and whose use has become critical with the evolution of silicon wafer size standards (M2–M10). Fortunately, the recent concept of 6'' half-cut cell with its many advantages appears promising insofar as it offers the possibility of further extend the use of costly, still operational process equipment, but doomed to obsolescence. Design/methodology/approach In the background of a detailed Al-BSF process, the authors show how to experimentally adapt specific accessories and arrange 6” half-wafers to enable the upgrade of a complete industrial process of silicon solar cells at a lower cost. Step by step, the implementation of the processes for the two wafer sizes (4” wafers and 6” half wafers) is compared and analyzed in terms of performance and throughput. Findings Globally, the same process effectiveness is observed for both types of wafers with slightly better sheet resistance uniformity for the thermal diffusion carried out on the half wafers; however, the horizontal arrangement of the wafer carriers in the diffusion and the plasma-enhanced chemical vapor deposition tubes limits the thermal balance regarding the total number of cells processed per batch. Originality/value In terms of the development of prototypes on a preindustrial scale, this paves the way to further continue operating outdated equipment for high-performance processes (passivated emitter and rear contact, Tunnel oxide passivated contact (TOPCon)), while complying with current standards for silicon wafers up to M10 format.
ISSN:1356-5362
1758-812X
DOI:10.1108/MI-09-2020-0065