A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment

Summary Presented in this paper is a new hardware architecture of the adaptive vector median filter (AVMF). The suggested structure yielded important values in impulsive noise removal from color images while preserving their fine details. The software (SW) study of this filter demonstrated that its implementation is too complex. To overcome this limitation, some approximations using a ROM memory were proposed to perform the square root for a hardware (HW) implementation. Comparative results between the ideal and approximated SWs of the AVMF showed a relative error equal to 0.01%. Then, sequential and parallel HW architectures were developed for this filter based on the approximated method. Finally, the validation of these architectures was conducted using an field‐programmable gate array (FPGA) platform on an HW/SW environment. The validation results demonstrated that the proposed HW/SW implementation of the AVMF can speed up the execution time 180 times in the worst case at 140 MHz compared to the SW solution as well as preserving a high data quality (same image quality). This paper presents a new hardware architecture of the adaptive vector median filter (AVMF). Sequential and parallel hardware architectures were developed for this filter based on the approximated method for the square root. The validation of these architectures was conducted using an FPGA platform on an HW/SW environment. The validation results demonstrated that the proposed HW/SW implementation of the AVMF can speed up the execution time 180 times in the worst case at 140 MHz compared to the SW solution as well as preserving a high data quality (same image quality).