An improved algorithm for accelerating reconfiguration of VLSI array

Reducing the number of visits to failure-free nodes can effectively reduce the reconstruction time of logical columns and improve the reconstruction efficiency. In this paper, we describe a new method to speed up the reconfiguration for the VLSI arrays. An efficient algorithm was proposed based on shortest path first principle for accelerating reconfiguration of VLSI processor subarrays with high power efficiency to meet the requirement of the power consumption of embedded system. The proposed algorithm greatly reduces the number of visits to the fault-free PEs for constructing a local optimal logical column and effectively reduces the construction time. Experimental results show that the proposed algorithm is capable of reducing the consumption time by 32.15% and reducing the numbers of visited PEs by 49.61% for a 128 × 128 host array with 20% falut rate. •We propose an algorithm based on shortest-path-first, which effectively reduce the number of visited PEs.•We prove that the time complexity of the algorithm is lower than that of previous algorithms.•We show that the scheme effectively reduces the time of reconfiguration and get the subarray in polynomial time.