Efficient design of decimation filter using linear programming and its FPGA implementation

In this paper we present two-stage CIC (cascaded-integrator-comb) decimation filters with decimation factor M expressed as M = M1M2, where M1,M2∈Z+. The proposed decimator-I aims to minimize the pass-band droop using a cascade connection of Kaiser Hamming (KH) and Saramäki-Ritoniemi (SR) sharpening structures. The coefficients of second stage are determined using linear programming in MATLAB. The proposed CIC decimator-I when designed for various integer decimation factors on an average has a pass-band droop of −0.09 dB at the normalized frequency of 1/2 M and an average alias rejection of −44 dB at the normalized frequency of 3/2 M. Further, another decimator-II structure extends decimator-I to achieve an alias rejection of −87 dB and pass-band droop of −0.17 dB. The FPGA implementation of proposed designs has lower slice utilization and achieves higher maximum operating frequency than other existing competing designs. The performance of proposed decimation filters is confirmed using computer simulations in analog-to-digital converters (ADC) and sigma-delta (ΣΔ) modulators. •The paper deals with CIC decimation filter which is active area of research in the domain of signal processing.•he main novelty of the paper lies in its capability of achieving the lowest pass-band droop amongst the current state-of-art designs while still having considerable high alias rejection.•The design is verified using simulations and two applications of CIC decimation filters, ADC and sigma-delta modulators.•The decimation structure and sharpening coefficients are independent of the decimation factor.•The proposed filter under all conditions has unity gain in the pass-band which facilitates fixed-point hardware implementation.