Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals

Electroencephalogram (EEG) is a biomedical technique for capturing the human brain’s electrical information to process its activities and actions. EEG is one of the main methods commonly used in neuroscience, from clinical analysis to the design of brain–computer interfaces. The first one of the many challenges in an EEG system design regards the ultra-low amplitude of signals (i.e., of the order of 20 μ V ) and their susceptibility to several kinds of interferences. Electromagnetic interference (EMI) omnidirectionally irradiated by the power line supplies disturbs the EEG instrumentation system with a noise power mostly concentrated from 50 to 60 Hz . Our paper investigates the energy efficiency of adaptive filtering (AF) techniques based on the least mean square (LMS), normalized LMS, and set-membership (SM) families for meeting the protection against EMI in EEG systems. The results demonstrate that the LMS algorithm presents an unstable behavior with unsatisfactory results against the normalized LMS filters when subject to noisy scenarios. Therefore, we herein explore dedicated VLSI hardware architectures for the following filters: (a) normalized LMS (NLMS), (b) SM-NLMS, (c) partial update NLMS (PU-NLMS), and (d) SM bi-normalized LMS (SM-BNLMS). PU-NLMS architecture offers the best trade-off between the capability of eliminating the EMI versus its power dissipation, circuit area, and maximum clock frequency. PU-NLMS provides an artifact reduction level of up to 8.8 dB , with low energy consumption of 0.62 nJ/operation and just 1.41 % larger circuit area than the NLMS architecture.