DC and transient models of the MSET device

As a multigate device, the multiple‐state electrostatically formed nanowire transistor (MSET) exhibits a rather complex characteristic on account of the coupling between each of its two adjacent terminals. The MSET has shown promise across a steadily growing range of applications and integrated circuit components. However, an analytical model of the MSET has not been formulated. The objective of this work was to develop practical DC and transient models of the MSET. The modeling approach comprises two stages: the first stage consists of a bottom‐up derivation of the I–V characteristics from the fundamental physical level using the physical processes within the device to derive equations that describe its steady‐state behavior; the second stage proposes a set of analytical equations more applicable to simulation environments. A transient model that considers device parasitic capacitance is also established. The models are validated against robust model simulations in TCAD Sentaurus and Cadence Virtuoso.