UVM based verification of iAPX 186 processor modules

UVM is used to enable faster development and reuse of System Verilog based Verification Environment. The use of UVM is to develop reusable test bench. The UVM class library contains configuration database, TLM and component hierarchy. Each and every component in the verification environment has a specific functionality. The UVM has a list of base class which are pre-stored and System Verilog environment can be built by deriving the base classes. Two parameters have been used namely Coverage and Assertions. Coverage is used to measure whether all features of the design specification is tested. Assertions are used for checking the behavior of the design. In this work, we design the individual blocks like Interrupt Controller, Timer module, DMA Controller, Execution Unit and Bus Interface Unit of 80186 processor using Verilog and Verify its functionality behavior using the two parameters using UVM.