2×VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

Since the CMOS technology moving forward swiftly, digital data exchange between chips fabricated using different generations of technologies becomes a problem when the size of printed circuit board-based systems is critical for mobile or wearable devices. To achieve better performance, smaller size, and power efficiency, a 2 × VDD output buffer featured with process, voltage, and temperature detection and the integration of dual-Vth and standard Vth transistors optimized by W/L sizing is proposed. Slew rate (SR) self-adjustment and power–delay product reduction are also verified by Monte Carlo simulations to achieve at least 27.8% improvement and 37.6% reduction. The prototype of this investigation fabricated by a typical 28-nm CMOS process is measured on silicon to attain at least 7.6% SR improvement.