Design and implementation of a fast sequential multiplier based on iterative addition architecture

In this paper, a fast design and implementation for sequential multiplier is presented. The suggested approach of implementation incorporates a definition of iterative addition that reduces the number of additions required in calculating the product of two binary numbers. The proposed implementation of sequential multiplier eliminates all shift operations required by conventional sequential multiplier to only one shift operation with the final accumulated result. Proposed and conventional designs of sequential multiplier are simulated in Quartus II synthesis software tool using Verilog implementation. According to the simulation results, the proposed implementation of sequential multiplier is better than conventional implementation in terms of delay time and power consumption. The proposed sequential multiplier shows an average improvement of 17.15% in delay time compared to conventional sequential multiplier.