Efficient Implementation for PRINCE Algorithm in FPGA Based on the BB84 Protocol

The current study introduces a hardware-implemented PRINCE block cipher within Field Programmable Gate Array (FPGA) determined by the quantum cryptography protocol (BB84). Most security-related software applications of cryptographic algorithms tend to be rather slow and of no efficiency. So as to present a solution to this issue, a new hardware architecture is suggested for speeding up the execution of the PRINCE algorithm and increasing its flexibility, yet with more security. Concurrent computing designs allow an encryption block data of 64 bits during a single clock cycle, resulting in the reduction of hardware area and the production of a higher throughput and relatively lower latency. Higher speed processing and lower power consumption are other features that have been observed. This could be achieved by means of implementing the encrypting, decrypting and quantum key schedule using little hardware sources, followed by the development of a sufficient hardware architecture model for the PRINCE algorithm through very high speed integrated circuit hardware description language (VHDL). The synthetization of this VHDL design is eventually performed in FPGA boards. As for the present study, two FPGA boards have been employed, namely Virtex-4 and Kintex-7. The resulting data indicates the throughput and efficiency values to be (2.029 Gbps) and (1.9 Mbps/slice) for Virtex-4, and (3.931 Gbps) and (7.290 Mbps/slice) for Kintex-7, all respectively.