Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology

In advanced technology nodes, emerging 3-D integration technology is a promising "More Than Moore" lever for continued scaling of system capability and value. In the 3-D integrated circuit (3-D IC) implementation, the power delivery network (PDN) is crucial to meeting design specifications...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2021-04, Vol.29 (4), p.591-604
Hauptverfasser: Kahng, Andrew B., Kang, Seokhyeong, Kim, Seungwon, Xu, Bangqi
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 604
container_issue 4
container_start_page 591
container_title IEEE transactions on very large scale integration (VLSI) systems
container_volume 29
creator Kahng, Andrew B.
Kang, Seokhyeong
Kim, Seungwon
Xu, Bangqi
description In advanced technology nodes, emerging 3-D integration technology is a promising "More Than Moore" lever for continued scaling of system capability and value. In the 3-D integrated circuit (3-D IC) implementation, the power delivery network (PDN) is crucial to meeting design specifications. However, determining the optimal PDN design is nontrivial. On the one hand, to meet the voltage (IR) drop requirement, a denser power mesh is desired. On the other hand, to meet the timing requirement, more routing resource is needed for signal routing. Moreover, additional competition between signal routing and power routing is caused by intertier vertical interconnects in 3-D IC. In this article, we propose a power delivery pathfinding methodology for emerging 3-D integration, which seeks to identify a "near-optimal" (or, very high quality) PDN for a given BEOL stack, vertical interconnection, and PDN specification. Compared with previous works, our methodology can explore richer solution spaces as it supports different PDN layer combinations and PDN layer configurations. We develop models for routability and worst IR drop to help reduce iterations between PDN design and circuit design in 3-D IC implementation. We present validations and demonstrate improvement in IR drop and routability with real design blocks in 28- and 14-nm foundry technology nodes.
doi_str_mv 10.1109/TVLSI.2020.3041665
format Article
fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_2509075638</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9301200</ieee_id><sourcerecordid>2509075638</sourcerecordid><originalsourceid>FETCH-LOGICAL-c339t-fd3ed944261df725be12f35f931d19670806d933d79faf9498d36bbd11538a673</originalsourceid><addsrcrecordid>eNo9kFFPwjAQxxujiYh-AX1Z4vPw2lu79dEAKpFEEtHXpqztGIEWu6Hh2zuEeC93l_x_d8mPkFsKA0pBPsw_p--TAQMGA4SMCsHPSI9ynqeyq_NuBoFpwShckqumWQHQLJPQI69jv9S-tCaZhR8bk5Fd19827pOZbpeu9qb2VeJCTMYbG6vDgukomfjWVlG3dfDJ3JZLH9ah2l-TC6fXjb059T75eBrPhy_p9O15MnycpiWibFNn0BqZZUxQ43LGF5Yyh9xJpIZKkUMBwkhEk0unncxkYVAsFoZSjoUWOfbJ_fHuNoavnW1atQq76LuXinGQkHOBRZdix1QZQ9NE69Q21hsd94qCOkhTf9LUQZo6SeuguyNUW2v_AYlAGQD-Au6SZ1U</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2509075638</pqid></control><display><type>article</type><title>Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology</title><source>IEEE Electronic Library (IEL)</source><creator>Kahng, Andrew B. ; Kang, Seokhyeong ; Kim, Seungwon ; Xu, Bangqi</creator><creatorcontrib>Kahng, Andrew B. ; Kang, Seokhyeong ; Kim, Seungwon ; Xu, Bangqi</creatorcontrib><description>In advanced technology nodes, emerging 3-D integration technology is a promising "More Than Moore" lever for continued scaling of system capability and value. In the 3-D integrated circuit (3-D IC) implementation, the power delivery network (PDN) is crucial to meeting design specifications. However, determining the optimal PDN design is nontrivial. On the one hand, to meet the voltage (IR) drop requirement, a denser power mesh is desired. On the other hand, to meet the timing requirement, more routing resource is needed for signal routing. Moreover, additional competition between signal routing and power routing is caused by intertier vertical interconnects in 3-D IC. In this article, we propose a power delivery pathfinding methodology for emerging 3-D integration, which seeks to identify a "near-optimal" (or, very high quality) PDN for a given BEOL stack, vertical interconnection, and PDN specification. Compared with previous works, our methodology can explore richer solution spaces as it supports different PDN layer combinations and PDN layer configurations. We develop models for routability and worst IR drop to help reduce iterations between PDN design and circuit design in 3-D IC implementation. We present validations and demonstrate improvement in IR drop and routability with real design blocks in 28- and 14-nm foundry technology nodes.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2020.3041665</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>3-D integration ; Circuit design ; Design methodology ; Design specifications ; Electric potential ; Electric power ; Electricity generation ; Finite element method ; Integrated circuit modeling ; Integrated circuits ; Logic gates ; Nodes ; power delivery ; routability analysis ; Routing ; Solution space ; Specifications ; Stacking ; system pathfinding ; Through-silicon vias ; voltage (IR) drop prediction</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.591-604</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c339t-fd3ed944261df725be12f35f931d19670806d933d79faf9498d36bbd11538a673</citedby><cites>FETCH-LOGICAL-c339t-fd3ed944261df725be12f35f931d19670806d933d79faf9498d36bbd11538a673</cites><orcidid>0000-0003-3015-1806 ; 0000-0002-9016-8792 ; 0000-0001-6768-6201</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9301200$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9301200$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kahng, Andrew B.</creatorcontrib><creatorcontrib>Kang, Seokhyeong</creatorcontrib><creatorcontrib>Kim, Seungwon</creatorcontrib><creatorcontrib>Xu, Bangqi</creatorcontrib><title>Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>In advanced technology nodes, emerging 3-D integration technology is a promising "More Than Moore" lever for continued scaling of system capability and value. In the 3-D integrated circuit (3-D IC) implementation, the power delivery network (PDN) is crucial to meeting design specifications. However, determining the optimal PDN design is nontrivial. On the one hand, to meet the voltage (IR) drop requirement, a denser power mesh is desired. On the other hand, to meet the timing requirement, more routing resource is needed for signal routing. Moreover, additional competition between signal routing and power routing is caused by intertier vertical interconnects in 3-D IC. In this article, we propose a power delivery pathfinding methodology for emerging 3-D integration, which seeks to identify a "near-optimal" (or, very high quality) PDN for a given BEOL stack, vertical interconnection, and PDN specification. Compared with previous works, our methodology can explore richer solution spaces as it supports different PDN layer combinations and PDN layer configurations. We develop models for routability and worst IR drop to help reduce iterations between PDN design and circuit design in 3-D IC implementation. We present validations and demonstrate improvement in IR drop and routability with real design blocks in 28- and 14-nm foundry technology nodes.</description><subject>3-D integration</subject><subject>Circuit design</subject><subject>Design methodology</subject><subject>Design specifications</subject><subject>Electric potential</subject><subject>Electric power</subject><subject>Electricity generation</subject><subject>Finite element method</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuits</subject><subject>Logic gates</subject><subject>Nodes</subject><subject>power delivery</subject><subject>routability analysis</subject><subject>Routing</subject><subject>Solution space</subject><subject>Specifications</subject><subject>Stacking</subject><subject>system pathfinding</subject><subject>Through-silicon vias</subject><subject>voltage (IR) drop prediction</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kFFPwjAQxxujiYh-AX1Z4vPw2lu79dEAKpFEEtHXpqztGIEWu6Hh2zuEeC93l_x_d8mPkFsKA0pBPsw_p--TAQMGA4SMCsHPSI9ynqeyq_NuBoFpwShckqumWQHQLJPQI69jv9S-tCaZhR8bk5Fd19827pOZbpeu9qb2VeJCTMYbG6vDgukomfjWVlG3dfDJ3JZLH9ah2l-TC6fXjb059T75eBrPhy_p9O15MnycpiWibFNn0BqZZUxQ43LGF5Yyh9xJpIZKkUMBwkhEk0unncxkYVAsFoZSjoUWOfbJ_fHuNoavnW1atQq76LuXinGQkHOBRZdix1QZQ9NE69Q21hsd94qCOkhTf9LUQZo6SeuguyNUW2v_AYlAGQD-Au6SZ1U</recordid><startdate>20210401</startdate><enddate>20210401</enddate><creator>Kahng, Andrew B.</creator><creator>Kang, Seokhyeong</creator><creator>Kim, Seungwon</creator><creator>Xu, Bangqi</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-3015-1806</orcidid><orcidid>https://orcid.org/0000-0002-9016-8792</orcidid><orcidid>https://orcid.org/0000-0001-6768-6201</orcidid></search><sort><creationdate>20210401</creationdate><title>Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology</title><author>Kahng, Andrew B. ; Kang, Seokhyeong ; Kim, Seungwon ; Xu, Bangqi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c339t-fd3ed944261df725be12f35f931d19670806d933d79faf9498d36bbd11538a673</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>3-D integration</topic><topic>Circuit design</topic><topic>Design methodology</topic><topic>Design specifications</topic><topic>Electric potential</topic><topic>Electric power</topic><topic>Electricity generation</topic><topic>Finite element method</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuits</topic><topic>Logic gates</topic><topic>Nodes</topic><topic>power delivery</topic><topic>routability analysis</topic><topic>Routing</topic><topic>Solution space</topic><topic>Specifications</topic><topic>Stacking</topic><topic>system pathfinding</topic><topic>Through-silicon vias</topic><topic>voltage (IR) drop prediction</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kahng, Andrew B.</creatorcontrib><creatorcontrib>Kang, Seokhyeong</creatorcontrib><creatorcontrib>Kim, Seungwon</creatorcontrib><creatorcontrib>Xu, Bangqi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kahng, Andrew B.</au><au>Kang, Seokhyeong</au><au>Kim, Seungwon</au><au>Xu, Bangqi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2021-04-01</date><risdate>2021</risdate><volume>29</volume><issue>4</issue><spage>591</spage><epage>604</epage><pages>591-604</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>In advanced technology nodes, emerging 3-D integration technology is a promising "More Than Moore" lever for continued scaling of system capability and value. In the 3-D integrated circuit (3-D IC) implementation, the power delivery network (PDN) is crucial to meeting design specifications. However, determining the optimal PDN design is nontrivial. On the one hand, to meet the voltage (IR) drop requirement, a denser power mesh is desired. On the other hand, to meet the timing requirement, more routing resource is needed for signal routing. Moreover, additional competition between signal routing and power routing is caused by intertier vertical interconnects in 3-D IC. In this article, we propose a power delivery pathfinding methodology for emerging 3-D integration, which seeks to identify a "near-optimal" (or, very high quality) PDN for a given BEOL stack, vertical interconnection, and PDN specification. Compared with previous works, our methodology can explore richer solution spaces as it supports different PDN layer combinations and PDN layer configurations. We develop models for routability and worst IR drop to help reduce iterations between PDN design and circuit design in 3-D IC implementation. We present validations and demonstrate improvement in IR drop and routability with real design blocks in 28- and 14-nm foundry technology nodes.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2020.3041665</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0003-3015-1806</orcidid><orcidid>https://orcid.org/0000-0002-9016-8792</orcidid><orcidid>https://orcid.org/0000-0001-6768-6201</orcidid><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1063-8210
ispartof IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.591-604
issn 1063-8210
1557-9999
language eng
recordid cdi_proquest_journals_2509075638
source IEEE Electronic Library (IEL)
subjects 3-D integration
Circuit design
Design methodology
Design specifications
Electric potential
Electric power
Electricity generation
Finite element method
Integrated circuit modeling
Integrated circuits
Logic gates
Nodes
power delivery
routability analysis
Routing
Solution space
Specifications
Stacking
system pathfinding
Through-silicon vias
voltage (IR) drop prediction
title Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T20%3A24%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Enhanced%20Power%20Delivery%20Pathfinding%20for%20Emerging%203-D%20Integration%20Technology&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Kahng,%20Andrew%20B.&rft.date=2021-04-01&rft.volume=29&rft.issue=4&rft.spage=591&rft.epage=604&rft.pages=591-604&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2020.3041665&rft_dat=%3Cproquest_RIE%3E2509075638%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2509075638&rft_id=info:pmid/&rft_ieee_id=9301200&rfr_iscdi=true