Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

•A new statistical model for reliability estimation of FPGA-based designs.•Reliability estimation by taking both SBUs and MCUs into account.•Validating the proposed model using a fault simulation procedure.•Assessing the accuracy of the model using 95% confidence interval.•Demonstrating the importance of considering MCUs in the reliability estimation. This paper addresses the problem of hardware tasks reliability estimation in harsh environments. A novel statistical model is presented to estimate the reliability, the mean time to failure, and the number of errors of hardware tasks running on static random-access memory (SRAM)-based partially run-time reconfigurable field programmable gate arrays (FPGAs) in harsh environments by taking both single-bit upsets and multiple-cell upsets into account. The model requires some features of the hardware tasks, including their computation time, size, the percent of critical bits, and the soft error rates of k-bit events (k ≥ 1) of the environment for the reliability estimation. Such an early estimation helps the developers to assess the reliability of their designs at earlier stages and leads to reduce the development cost. The proposed model has been evaluated by conducting several experiments on actual hardware tasks over different environmental soft error rates. The obtained results, endorsed by the 95% confidence interval, reveal the high accuracy of the proposed model. When comparing this approach with a reliability model (developed by the authors in a previous work) that does not consider the occurrence of multiple-cell upsets, an overestimation of the mean time to failure of 2.88X is observable in the latter. This points to the importance of taking into account multiple events, especially in modern technologies where the miniaturization is high.