High energy-efficient switching scheme for SAR ADC with low common-mode level variation

This letter presents a novel high energy-efficient switching scheme with low common-mode level variation for successive approximation register (SAR) analog-to-digital converters. Benefit from the merge capacitor split and C-2C techniques, the proposed switching scheme achieves 98% saving in switching energy and 86.91% reduction in capacitor area over the conventional scheme without reset energy. Compared with state-of-the-art works, the area saving is the highest. Meanwhile, the common-mode level at the comparator input is V cm except the second cycle and the last cycle during SAR ADC conversion phase, which reduces the dynamic offset of the comparator greatly.