P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area

A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the developme...

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Veröffentlicht in:	SID International Symposium Digest of technical papers 2021-02, Vol.52 (S1), p.436-438
Hauptverfasser:	Xu, Shangjun, Wang, Mingxin, Wang, Zhijun, Zhou, Liufei, Shu, Yang, Yuan, Ling, Bian, Cunjian, Fei, Mi, Wang, Lizhong, Wang, Huaipei, Liu, Deyu
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitance Circuit design Driver circuits Gates (circuits) GOA in AA Lateral Capacitance Narrow Bezel
Online-Zugang:	Volltext
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