P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area

P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area

A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the developme...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:SID International Symposium Digest of technical papers 2021-02, Vol.52 (S1), p.436-438
Hauptverfasser: Xu, Shangjun, Wang, Mingxin, Wang, Zhijun, Zhou, Liufei, Shu, Yang, Yuan, Ling, Bian, Cunjian, Fei, Mi, Wang, Lizhong, Wang, Huaipei, Liu, Deyu
Format: Artikel
Sprache:eng
Schlagworte:
Capacitance
Circuit design
Driver circuits
Gates (circuits)
GOA in AA
Lateral Capacitance
Narrow Bezel
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the development of higher integrated and more intelligent panel in the future.
ISSN:0097-966X
2168-0159
DOI:10.1002/sdtp.14513