P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area
A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the developme...
Gespeichert in:
| Veröffentlicht in: | SID International Symposium Digest of technical papers 2021-02, Vol.52 (S1), p.436-438 |
|---|---|
| Hauptverfasser: | , , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 438 |
|---|---|
| container_issue | S1 |
| container_start_page | 436 |
| container_title | SID International Symposium Digest of technical papers |
| container_volume | 52 |
| creator | Xu, Shangjun Wang, Mingxin Wang, Zhijun Zhou, Liufei Shu, Yang Yuan, Ling Bian, Cunjian Fei, Mi Wang, Lizhong Wang, Huaipei Liu, Deyu |
| description | A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the development of higher integrated and more intelligent panel in the future. |
| doi_str_mv | 10.1002/sdtp.14513 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2492708700</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2492708700</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1413-fab2e1a4d6ece63f3eea713e35add5d6c74bc7c12b488033a2bfb10643d7b4b13</originalsourceid><addsrcrecordid>eNp9kMtOwzAQRS0EEqWw4QsssUNKsWPnxa5KH1SqRCWKxC5ynDE1Ckmw3Vbd8Ql8I1-CS1izmsU9d0ZzELqmZEQJCe9s5boR5RFlJ2gQ0jgNCI2yUzQgJEuCLI5fztGFtW-EMMZ5NkC71ffnFx1l93i9ATxVCqTDrcJL4cCIGueiE1I70UjAbYNntXC-sBIN1HiibVeLA95rt8FzX8ATo3dgcK6N3Gpn8aJx8Gp8UmHd4LF0PsZjA-ISnSlRW7j6m0P0PJuu84dg-Thf5ONlICmnLFCiDIEKXsUgIWaKAYiEMmCRqKqoimXCS5lIGpY8Tf1LIixVSUnMWZWUvKRsiG76vZ1pP7ZgXfHWbk3jTxYhz8KEpIlXMUS3PSVNa60BVXRGvwtzKCgpjl6Lo9fi16uHaQ_vdQ2Hf8jiabJe9Z0fux58hQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2492708700</pqid></control><display><type>article</type><title>P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area</title><source>Wiley Journals</source><creator>Xu, Shangjun ; Wang, Mingxin ; Wang, Zhijun ; Zhou, Liufei ; Shu, Yang ; Yuan, Ling ; Bian, Cunjian ; Fei, Mi ; Wang, Lizhong ; Wang, Huaipei ; Liu, Deyu</creator><creatorcontrib>Xu, Shangjun ; Wang, Mingxin ; Wang, Zhijun ; Zhou, Liufei ; Shu, Yang ; Yuan, Ling ; Bian, Cunjian ; Fei, Mi ; Wang, Lizhong ; Wang, Huaipei ; Liu, Deyu</creatorcontrib><description>A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the development of higher integrated and more intelligent panel in the future.</description><identifier>ISSN: 0097-966X</identifier><identifier>EISSN: 2168-0159</identifier><identifier>DOI: 10.1002/sdtp.14513</identifier><language>eng</language><publisher>Campbell: Wiley Subscription Services, Inc</publisher><subject>Capacitance ; Circuit design ; Driver circuits ; Gates (circuits) ; GOA in AA ; Lateral Capacitance ; Narrow Bezel</subject><ispartof>SID International Symposium Digest of technical papers, 2021-02, Vol.52 (S1), p.436-438</ispartof><rights>2021 The Society for Information Display</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1002%2Fsdtp.14513$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.1002%2Fsdtp.14513$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,780,784,1417,27924,27925,45574,45575</link.rule.ids></links><search><creatorcontrib>Xu, Shangjun</creatorcontrib><creatorcontrib>Wang, Mingxin</creatorcontrib><creatorcontrib>Wang, Zhijun</creatorcontrib><creatorcontrib>Zhou, Liufei</creatorcontrib><creatorcontrib>Shu, Yang</creatorcontrib><creatorcontrib>Yuan, Ling</creatorcontrib><creatorcontrib>Bian, Cunjian</creatorcontrib><creatorcontrib>Fei, Mi</creatorcontrib><creatorcontrib>Wang, Lizhong</creatorcontrib><creatorcontrib>Wang, Huaipei</creatorcontrib><creatorcontrib>Liu, Deyu</creatorcontrib><title>P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area</title><title>SID International Symposium Digest of technical papers</title><description>A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the development of higher integrated and more intelligent panel in the future.</description><subject>Capacitance</subject><subject>Circuit design</subject><subject>Driver circuits</subject><subject>Gates (circuits)</subject><subject>GOA in AA</subject><subject>Lateral Capacitance</subject><subject>Narrow Bezel</subject><issn>0097-966X</issn><issn>2168-0159</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><recordid>eNp9kMtOwzAQRS0EEqWw4QsssUNKsWPnxa5KH1SqRCWKxC5ynDE1Ckmw3Vbd8Ql8I1-CS1izmsU9d0ZzELqmZEQJCe9s5boR5RFlJ2gQ0jgNCI2yUzQgJEuCLI5fztGFtW-EMMZ5NkC71ffnFx1l93i9ATxVCqTDrcJL4cCIGueiE1I70UjAbYNntXC-sBIN1HiibVeLA95rt8FzX8ATo3dgcK6N3Gpn8aJx8Gp8UmHd4LF0PsZjA-ISnSlRW7j6m0P0PJuu84dg-Thf5ONlICmnLFCiDIEKXsUgIWaKAYiEMmCRqKqoimXCS5lIGpY8Tf1LIixVSUnMWZWUvKRsiG76vZ1pP7ZgXfHWbk3jTxYhz8KEpIlXMUS3PSVNa60BVXRGvwtzKCgpjl6Lo9fi16uHaQ_vdQ2Hf8jiabJe9Z0fux58hQ</recordid><startdate>202102</startdate><enddate>202102</enddate><creator>Xu, Shangjun</creator><creator>Wang, Mingxin</creator><creator>Wang, Zhijun</creator><creator>Zhou, Liufei</creator><creator>Shu, Yang</creator><creator>Yuan, Ling</creator><creator>Bian, Cunjian</creator><creator>Fei, Mi</creator><creator>Wang, Lizhong</creator><creator>Wang, Huaipei</creator><creator>Liu, Deyu</creator><general>Wiley Subscription Services, Inc</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>202102</creationdate><title>P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area</title><author>Xu, Shangjun ; Wang, Mingxin ; Wang, Zhijun ; Zhou, Liufei ; Shu, Yang ; Yuan, Ling ; Bian, Cunjian ; Fei, Mi ; Wang, Lizhong ; Wang, Huaipei ; Liu, Deyu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1413-fab2e1a4d6ece63f3eea713e35add5d6c74bc7c12b488033a2bfb10643d7b4b13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Capacitance</topic><topic>Circuit design</topic><topic>Driver circuits</topic><topic>Gates (circuits)</topic><topic>GOA in AA</topic><topic>Lateral Capacitance</topic><topic>Narrow Bezel</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Xu, Shangjun</creatorcontrib><creatorcontrib>Wang, Mingxin</creatorcontrib><creatorcontrib>Wang, Zhijun</creatorcontrib><creatorcontrib>Zhou, Liufei</creatorcontrib><creatorcontrib>Shu, Yang</creatorcontrib><creatorcontrib>Yuan, Ling</creatorcontrib><creatorcontrib>Bian, Cunjian</creatorcontrib><creatorcontrib>Fei, Mi</creatorcontrib><creatorcontrib>Wang, Lizhong</creatorcontrib><creatorcontrib>Wang, Huaipei</creatorcontrib><creatorcontrib>Liu, Deyu</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>SID International Symposium Digest of technical papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Xu, Shangjun</au><au>Wang, Mingxin</au><au>Wang, Zhijun</au><au>Zhou, Liufei</au><au>Shu, Yang</au><au>Yuan, Ling</au><au>Bian, Cunjian</au><au>Fei, Mi</au><au>Wang, Lizhong</au><au>Wang, Huaipei</au><au>Liu, Deyu</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area</atitle><jtitle>SID International Symposium Digest of technical papers</jtitle><date>2021-02</date><risdate>2021</risdate><volume>52</volume><issue>S1</issue><spage>436</spage><epage>438</epage><pages>436-438</pages><issn>0097-966X</issn><eissn>2168-0159</eissn><abstract>A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the development of higher integrated and more intelligent panel in the future.</abstract><cop>Campbell</cop><pub>Wiley Subscription Services, Inc</pub><doi>10.1002/sdtp.14513</doi><tpages>3</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0097-966X |
| ispartof | SID International Symposium Digest of technical papers, 2021-02, Vol.52 (S1), p.436-438 |
| issn | 0097-966X 2168-0159 |
| language | eng |
| recordid | cdi_proquest_journals_2492708700 |
| source | Wiley Journals |
| subjects | Capacitance Circuit design Driver circuits Gates (circuits) GOA in AA Lateral Capacitance Narrow Bezel |
| title | P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T14%3A51%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=P%E2%80%901.9:%20The%20Effect%20of%20Lateral%20Capacitance%20on%20Flat%E2%80%90Panel%20Display%20with%20Gate%20Driver%20Circuits%20Integrated%20in%20Active%20Area&rft.jtitle=SID%20International%20Symposium%20Digest%20of%20technical%20papers&rft.au=Xu,%20Shangjun&rft.date=2021-02&rft.volume=52&rft.issue=S1&rft.spage=436&rft.epage=438&rft.pages=436-438&rft.issn=0097-966X&rft.eissn=2168-0159&rft_id=info:doi/10.1002/sdtp.14513&rft_dat=%3Cproquest_cross%3E2492708700%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2492708700&rft_id=info:pmid/&rfr_iscdi=true |