PI-Based Synchronous Reference Frame Frequency-Locked Loop
A novel proportional-integral (PI)-based frequency-locked loop (FLL) is proposed and verified in this letter. Unlike the conventional FLL, which is implemented in the stationary ( αβ ) reference frame, the proposed PI-based FLL (PI-FLL) is implemented in the synchronous ( dq ) reference frame. A Lya...
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| Veröffentlicht in: | IEEE transactions on industrial electronics (1982) 2021-05, Vol.68 (5), p.4547-4553 |
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| container_title | IEEE transactions on industrial electronics (1982) |
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| creator | Quan, Xiangjun Huang, Alex Q. |
| description | A novel proportional-integral (PI)-based frequency-locked loop (FLL) is proposed and verified in this letter. Unlike the conventional FLL, which is implemented in the stationary ( αβ ) reference frame, the proposed PI-based FLL (PI-FLL) is implemented in the synchronous ( dq ) reference frame. A Lyapunov candidate is constructed to prove the stability of the PI-FLL. In addition, a linear model is established to facilitate the parameter design of the PI-FLL. With the selected parameters, the performance of the proposed FLL is improved. Finally, the proposed PI-FLL is experimentally verified on a testbed using a 32-bit floating-point digital signal processor TMS320F28379D at 200 MHz. |
| doi_str_mv | 10.1109/TIE.2020.2985002 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_2488745213</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9059038</ieee_id><sourcerecordid>2488745213</sourcerecordid><originalsourceid>FETCH-LOGICAL-c291t-a9ee7bf17546c95604637d1f26687de3a2c9aae95b29aa6b52051779702c45f3</originalsourceid><addsrcrecordid>eNo9kEFLAzEQhYMoWKt3wUvBc-okm9kk3rS0WlhQtPeQprPYajc1aQ_996a0eJnHwHszj4-xWwFDIcA-zKbjoQQJQ2kNAsgz1hOImlurzDnrgdSGA6j6kl3lvAIQCgX22OP7lD_7TIvB574LXyl2cZcHH9RSoi7QYJL8-jDpd1f2PW9i-C7mJsbNNbto_U-mm5P22Wwyno1eefP2Mh09NTxIK7bcWyI9b4VGVQeLdelQ6YVoZV0bvaDKy2C9J4tzWbSeowQUWlsNMihsqz67P57dpFhK5K1bxV3qykcnlTFaoRRVccHRFVLMOVHrNmm59mnvBLgDIFcAuQMgdwJUInfHyJKI_u0W0EJlqj-6Ll9X</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2488745213</pqid></control><display><type>article</type><title>PI-Based Synchronous Reference Frame Frequency-Locked Loop</title><source>IEEE Electronic Library (IEL)</source><creator>Quan, Xiangjun ; Huang, Alex Q.</creator><creatorcontrib>Quan, Xiangjun ; Huang, Alex Q.</creatorcontrib><description>A novel proportional-integral (PI)-based frequency-locked loop (FLL) is proposed and verified in this letter. Unlike the conventional FLL, which is implemented in the stationary ( αβ ) reference frame, the proposed PI-based FLL (PI-FLL) is implemented in the synchronous ( dq ) reference frame. A Lyapunov candidate is constructed to prove the stability of the PI-FLL. In addition, a linear model is established to facilitate the parameter design of the PI-FLL. With the selected parameters, the performance of the proposed FLL is improved. Finally, the proposed PI-FLL is experimentally verified on a testbed using a 32-bit floating-point digital signal processor TMS320F28379D at 200 MHz.</description><identifier>ISSN: 0278-0046</identifier><identifier>EISSN: 1557-9948</identifier><identifier>DOI: 10.1109/TIE.2020.2985002</identifier><identifier>CODEN: ITIED6</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Complex filter ; Design parameters ; Digital signal processors ; Floating point arithmetic ; Frequency estimation ; Frequency locked loops ; Frequency locking ; Frequency synchronization ; frequency-locked loop (FLL) ; inverter control ; Microprocessors ; Nonlinear dynamical systems ; Phase locked loops ; phase-locked loop (PLL) ; Power system stability ; Signal processing ; Stability analysis ; synchronization</subject><ispartof>IEEE transactions on industrial electronics (1982), 2021-05, Vol.68 (5), p.4547-4553</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-a9ee7bf17546c95604637d1f26687de3a2c9aae95b29aa6b52051779702c45f3</citedby><cites>FETCH-LOGICAL-c291t-a9ee7bf17546c95604637d1f26687de3a2c9aae95b29aa6b52051779702c45f3</cites><orcidid>0000-0001-7926-0013 ; 0000-0003-3427-0335</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9059038$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9059038$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Quan, Xiangjun</creatorcontrib><creatorcontrib>Huang, Alex Q.</creatorcontrib><title>PI-Based Synchronous Reference Frame Frequency-Locked Loop</title><title>IEEE transactions on industrial electronics (1982)</title><addtitle>TIE</addtitle><description>A novel proportional-integral (PI)-based frequency-locked loop (FLL) is proposed and verified in this letter. Unlike the conventional FLL, which is implemented in the stationary ( αβ ) reference frame, the proposed PI-based FLL (PI-FLL) is implemented in the synchronous ( dq ) reference frame. A Lyapunov candidate is constructed to prove the stability of the PI-FLL. In addition, a linear model is established to facilitate the parameter design of the PI-FLL. With the selected parameters, the performance of the proposed FLL is improved. Finally, the proposed PI-FLL is experimentally verified on a testbed using a 32-bit floating-point digital signal processor TMS320F28379D at 200 MHz.</description><subject>Complex filter</subject><subject>Design parameters</subject><subject>Digital signal processors</subject><subject>Floating point arithmetic</subject><subject>Frequency estimation</subject><subject>Frequency locked loops</subject><subject>Frequency locking</subject><subject>Frequency synchronization</subject><subject>frequency-locked loop (FLL)</subject><subject>inverter control</subject><subject>Microprocessors</subject><subject>Nonlinear dynamical systems</subject><subject>Phase locked loops</subject><subject>phase-locked loop (PLL)</subject><subject>Power system stability</subject><subject>Signal processing</subject><subject>Stability analysis</subject><subject>synchronization</subject><issn>0278-0046</issn><issn>1557-9948</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEFLAzEQhYMoWKt3wUvBc-okm9kk3rS0WlhQtPeQprPYajc1aQ_996a0eJnHwHszj4-xWwFDIcA-zKbjoQQJQ2kNAsgz1hOImlurzDnrgdSGA6j6kl3lvAIQCgX22OP7lD_7TIvB574LXyl2cZcHH9RSoi7QYJL8-jDpd1f2PW9i-C7mJsbNNbto_U-mm5P22Wwyno1eefP2Mh09NTxIK7bcWyI9b4VGVQeLdelQ6YVoZV0bvaDKy2C9J4tzWbSeowQUWlsNMihsqz67P57dpFhK5K1bxV3qykcnlTFaoRRVccHRFVLMOVHrNmm59mnvBLgDIFcAuQMgdwJUInfHyJKI_u0W0EJlqj-6Ll9X</recordid><startdate>20210501</startdate><enddate>20210501</enddate><creator>Quan, Xiangjun</creator><creator>Huang, Alex Q.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-7926-0013</orcidid><orcidid>https://orcid.org/0000-0003-3427-0335</orcidid></search><sort><creationdate>20210501</creationdate><title>PI-Based Synchronous Reference Frame Frequency-Locked Loop</title><author>Quan, Xiangjun ; Huang, Alex Q.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-a9ee7bf17546c95604637d1f26687de3a2c9aae95b29aa6b52051779702c45f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Complex filter</topic><topic>Design parameters</topic><topic>Digital signal processors</topic><topic>Floating point arithmetic</topic><topic>Frequency estimation</topic><topic>Frequency locked loops</topic><topic>Frequency locking</topic><topic>Frequency synchronization</topic><topic>frequency-locked loop (FLL)</topic><topic>inverter control</topic><topic>Microprocessors</topic><topic>Nonlinear dynamical systems</topic><topic>Phase locked loops</topic><topic>phase-locked loop (PLL)</topic><topic>Power system stability</topic><topic>Signal processing</topic><topic>Stability analysis</topic><topic>synchronization</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Quan, Xiangjun</creatorcontrib><creatorcontrib>Huang, Alex Q.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on industrial electronics (1982)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Quan, Xiangjun</au><au>Huang, Alex Q.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>PI-Based Synchronous Reference Frame Frequency-Locked Loop</atitle><jtitle>IEEE transactions on industrial electronics (1982)</jtitle><stitle>TIE</stitle><date>2021-05-01</date><risdate>2021</risdate><volume>68</volume><issue>5</issue><spage>4547</spage><epage>4553</epage><pages>4547-4553</pages><issn>0278-0046</issn><eissn>1557-9948</eissn><coden>ITIED6</coden><abstract>A novel proportional-integral (PI)-based frequency-locked loop (FLL) is proposed and verified in this letter. Unlike the conventional FLL, which is implemented in the stationary ( αβ ) reference frame, the proposed PI-based FLL (PI-FLL) is implemented in the synchronous ( dq ) reference frame. A Lyapunov candidate is constructed to prove the stability of the PI-FLL. In addition, a linear model is established to facilitate the parameter design of the PI-FLL. With the selected parameters, the performance of the proposed FLL is improved. Finally, the proposed PI-FLL is experimentally verified on a testbed using a 32-bit floating-point digital signal processor TMS320F28379D at 200 MHz.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TIE.2020.2985002</doi><tpages>7</tpages><orcidid>https://orcid.org/0000-0001-7926-0013</orcidid><orcidid>https://orcid.org/0000-0003-3427-0335</orcidid></addata></record> |
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| subjects | Complex filter Design parameters Digital signal processors Floating point arithmetic Frequency estimation Frequency locked loops Frequency locking Frequency synchronization frequency-locked loop (FLL) inverter control Microprocessors Nonlinear dynamical systems Phase locked loops phase-locked loop (PLL) Power system stability Signal processing Stability analysis synchronization |
| title | PI-Based Synchronous Reference Frame Frequency-Locked Loop |
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