A Review of Wafer Packing and New Results: Examining Optimal Die Placement

This article reviews the waferpacking problem, which combines gross die per wafer (GDW) estimation and its associated optimal die-placement problems. It has been reported in the literature that there is limited set of possible die-placement schemes under regular die placement; the mathematical models used to compute GDW for each regular die-placement scheme are presented in this article. As a result, optimal wafer packing (the maximum number of GDWs) and its associated die-placement scheme can be obtained by comparing all GDWs obtained from this limited set of die placements. This article further investigates a particular irregular die placement commonly applied in devices fabricated in expensive substrates to achieve a higher GDW when compared to that of regular die-placement schemes. At the same time, a simple GDW approximation formula is presented and shown to be able to obtain a close approximation to the optimal GDW within 5% accuracy, in general. Furthermore, when the length of the long side of the die to the effective radius of the wafer is smaller than 1%, the estimation accuracy will be almost certain to improve to higher than 99% in most cases. Such a simple GDW estimation equation can be an effective tool to estimate engineering and costs for application- specific IC businesses.