Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression

In embedded graphics systems, the graphics processing unit (GPU) also consumes significant amount of frame buffer memory bandwidth. Frame buffer compression is widely adopted to alleviate both memory bandwidth and power consumption issues for the display controller, but rarely has it been applied to addressing GPU’s consumption. This paper proposes a real-time fixed-ratio frame buffer compression technique for RISC-V processor-based embedded graphics systems. The advantage of the proposed method is that the fixed-ratio compressed frame buffer can be directly adopted as an input texture by GPU. The proposed architecture (called an FBC coprocessor) is a hardware extension to the RISC-V microprocessor that supports frame buffer memory bandwidth reduction. The results show that the coprocessor consumes only 1% additional silicon space of the whole system, while reducing bandwidth consumption by 72.64%. A prototype system-on-a-chip indicates that the proposed FBC coprocessor can reduce GPU power consumption by up to 12.7% for an example automotive application.