Ultra-Low Power CMOS Image Sensor With Two-Step Logical Shift Algorithm-Based Correlated Double Sampling Scheme

This article presents an ultra-low power counter structure for a column-parallel single-slope analog-to-digital converter (SS-ADC) in CMOS image sensors. The proposed counter employs a two-step logical shift algorithm-based correlated double sampling (CDS) scheme. The logical shift algorithm can reduce parasitic capacitances, driving frequency, and inner toggling nodes by using the minimum number of transistors and a single-direction counter structure. Moreover, the two-step counting and double data rate scheme in the LSB counter can halve the operating clock frequency, resulting in further decreased power consumption. A prototype sensor was fabricated using a 110 nm CMOS image sensor process. The measurement results show that the proposed SS-ADC with a two-step counter consumes 2.4~\mu \text{W} power per column and shows a differential nonlinearity of +0.38/−0.25 LSB and an integral nonlinearity of +0.75/−0.5 LSB. The total power consumption is 2.25 mW for 640 \times 480 effective image resolution at 60 frame rates with 3.3 V/1.5 V supply voltage.