Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis

Recently, a compact realization of logic gates using double-gate tunnel field effect transistors (DGTFETs) with independently-controlled gate has been proposed. The key elements in the proposed implementation are the suppression of the tunneling at the surface using gate-source overlap and enable tunneling inside the TFET body by choosing appropriate silicon body thickness. Though these implementations are compact, our study reveals that there are a few critical problems: high average subthreshold swing ( SS_{avg} ), low ON-state current ( I_{ON} ) and large propagation delay ( t_{pd} ). In this paper, we examine the root cause of these problems and explore solutions to tackle them. It is demonstrated that the techniques that boost the I_{ON} in a TFET do not necessarily increase the I_{ON}/I_{OFF} ratio in the proposed implementations. The efficacy of these techniques in improving the I_{ON}/I_{OFF} ratio depends on whether the gate-source overlap is able to suppress the tunneling at the surface and restrict the OFF-state current ( I_{OFF} ). Furthermore, it is demonstrated that, for the AND functionality, compared to a purely silicon-based DGTFET (Si-TFET) employing silicon-germanium heterojunction DGTFET (HJ-TFET) results in an increase in the I_{ON} by 143 \times , an increase in the I_{ON}/I_{OFF} ratio by two orders of magnitude and an improvement in the SS_{avg} by 45%, at V_{DD}=0.6\,\,V . Moreover, a compact NAND gate realized using the proposed HJ-TFETs exhibits two orders of magnitude lower t_{pd} , compared to the NAND gate