Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology

This work concentrate on the design of low power substitution box architecture with enhanced galois field based transform towards multiplier in advanced cryptographic encryption core. Basic components such as AND, XOR, XNOR are being used for the designing process. Initially tree based XNOR gates ar...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	Microprocessors and microsystems 2020-04, Vol.74, p.103000, Article 103000
Hauptverfasser:	Nandan, V., Gowri Shankar Rao, R.
Format:	Artikel
Sprache:	eng
Schlagworte:	180 nm CMOS AES Architecture CMOS Cryptography Encryption Gates (circuits) Logic circuits Logic gates Power consumption Semiconductor devices Transistors XNOR gate
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!