Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology

This work concentrate on the design of low power substitution box architecture with enhanced galois field based transform towards multiplier in advanced cryptographic encryption core. Basic components such as AND, XOR, XNOR are being used for the designing process. Initially tree based XNOR gates are picked up and then the AND gates are replaced by NAND gated with less number of transistor in it. Here, logical method is carried out, which is actually considered as better method for re-sizing of transistor. This will further decrease the overall delay and power consumption. The less delay can be obtained by 4-input XOR gate architecture. The implementation results with an 180 nm CMOS standard library show that the proposed AES core can reduce the area and power consumption significantly.