Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology
This work concentrate on the design of low power substitution box architecture with enhanced galois field based transform towards multiplier in advanced cryptographic encryption core. Basic components such as AND, XOR, XNOR are being used for the designing process. Initially tree based XNOR gates ar...
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| Veröffentlicht in: | Microprocessors and microsystems 2020-04, Vol.74, p.103000, Article 103000 |
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| creator | Nandan, V. Gowri Shankar Rao, R. |
| description | This work concentrate on the design of low power substitution box architecture with enhanced galois field based transform towards multiplier in advanced cryptographic encryption core. Basic components such as AND, XOR, XNOR are being used for the designing process. Initially tree based XNOR gates are picked up and then the AND gates are replaced by NAND gated with less number of transistor in it. Here, logical method is carried out, which is actually considered as better method for re-sizing of transistor. This will further decrease the overall delay and power consumption. The less delay can be obtained by 4-input XOR gate architecture. The implementation results with an 180 nm CMOS standard library show that the proposed AES core can reduce the area and power consumption significantly. |
| doi_str_mv | 10.1016/j.micpro.2020.103000 |
| format | Article |
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The implementation results with an 180 nm CMOS standard library show that the proposed AES core can reduce the area and power consumption significantly.</description><subject>180 nm CMOS</subject><subject>AES</subject><subject>Architecture</subject><subject>CMOS</subject><subject>Cryptography</subject><subject>Encryption</subject><subject>Gates (circuits)</subject><subject>Logic circuits</subject><subject>Logic gates</subject><subject>Power consumption</subject><subject>Semiconductor devices</subject><subject>Transistors</subject><subject>XNOR gate</subject><issn>0141-9331</issn><issn>1872-9436</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><recordid>eNp9kEtPwzAQhC0EEqXwDzhY4pziV9zkglRV5SFR9dDeLcdZF0dpXOyUqvx6XMKZy660mpnVfAjdUzKhhMrHZrJzZh_8hBF2PnFCyAUa0WLKslJweYlGhAqalZzTa3QTY5MEOZFshPTSdW7nvnXvfIe9xbXbul63uPVbZ_BW9xCx7mp8aPugs9Yf8d4fIeDZYo2hM-G0_3UaHwC7DtOCzJerNe7BfHQ-hZxu0ZXVbYS7vz1Gm-fFZv6ava9e3uaz98xwLvoMGAWWU06tFbkteVlpVknGJeFGFCRpLFg21WloYYiFmpekElUt6NTmOR-jhyE2cfg8QOxV4w-hSx8VE7kQspCySCoxqEzwMQawah_cToeTokSdWapGDSzVmaUaWCbb02CDVODLQVDRuNQeahfA9Kr27v-AH-Nffjc</recordid><startdate>202004</startdate><enddate>202004</enddate><creator>Nandan, V.</creator><creator>Gowri Shankar Rao, R.</creator><general>Elsevier B.V</general><general>Elsevier BV</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>202004</creationdate><title>Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology</title><author>Nandan, V. ; Gowri Shankar Rao, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c334t-e21e25131ff45f939ba2b623603c480334fef27aef2a4c0fed390b4bd417f553</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>180 nm CMOS</topic><topic>AES</topic><topic>Architecture</topic><topic>CMOS</topic><topic>Cryptography</topic><topic>Encryption</topic><topic>Gates (circuits)</topic><topic>Logic circuits</topic><topic>Logic gates</topic><topic>Power consumption</topic><topic>Semiconductor devices</topic><topic>Transistors</topic><topic>XNOR gate</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Nandan, V.</creatorcontrib><creatorcontrib>Gowri Shankar Rao, R.</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Microprocessors and microsystems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Nandan, V.</au><au>Gowri Shankar Rao, R.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology</atitle><jtitle>Microprocessors and microsystems</jtitle><date>2020-04</date><risdate>2020</risdate><volume>74</volume><spage>103000</spage><pages>103000-</pages><artnum>103000</artnum><issn>0141-9331</issn><eissn>1872-9436</eissn><abstract>This work concentrate on the design of low power substitution box architecture with enhanced galois field based transform towards multiplier in advanced cryptographic encryption core. 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| issn | 0141-9331 1872-9436 |
| language | eng |
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| source | Elsevier ScienceDirect Journals |
| subjects | 180 nm CMOS AES Architecture CMOS Cryptography Encryption Gates (circuits) Logic circuits Logic gates Power consumption Semiconductor devices Transistors XNOR gate |
| title | Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology |
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