P‐36: Highly Reliable a‐IGZO TFT Gate Driver Circuit to Prevent Leakage Path in Depletion Mode Operation

P‐36: Highly Reliable a‐IGZO TFT Gate Driver Circuit to Prevent Leakage Path in Depletion Mode Operation

This paper proposes new gate driver circuit to prevent VOUT ripple voltage by boosting‐down effect of pull‐up unit. Using only one pull‐down TFT with 50% turn‐on duty ratio, the proposed circuit can obtain high reliability for continuous bias stress and fully cut‐off ripple voltage by negative VGS f...

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Veröffentlicht in:SID International Symposium Digest of technical papers 2020-08, Vol.51 (1), p.1486-1489
Hauptverfasser: Lee, Jungwoo, Oh, Jongsu, Jung, Eun Kyo, Park, KeeChan, Lee, Soo-Yeon, Kim, Yong-Sang
Format: Artikel
Sprache:eng
Schlagworte:
Circuit reliability
Depletion
Depletion Mode
Driver circuits
Duty Ratio
Electric potential
Gate Driver Circuit
Gates (circuits)
Indium gallium zinc oxide
Leakage Current
Oxide TFT
Reliability
Ripples
Voltage
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Beschreibung
Zusammenfassung:This paper proposes new gate driver circuit to prevent VOUT ripple voltage by boosting‐down effect of pull‐up unit. Using only one pull‐down TFT with 50% turn‐on duty ratio, the proposed circuit can obtain high reliability for continuous bias stress and fully cut‐off ripple voltage by negative VGS for pull‐up TFT.
ISSN:0097-966X
2168-0159
DOI:10.1002/sdtp.14168