A reusable stage based reduced comparator count binary search ADC

A 4- bit reusable stage based asynchronous binary search analog to digital converter (ADC) with a smart switching network, and reduced comparator count is presented in this paper. The proposed ADC uses asynchronous logic to activate comparators sequentially while switching network is used to provide reference voltages for selected comparators. In the extended version, the 6-bit ADC is designed using only ( N + 1 ) comparators instead of 2 ( N ) - 1 and (2N − 1) as used in conventional approach. The simulation results of 4 bit ADC confirms that the design achieves conversion speed of 500 MSPS with power consumption of 1.63 mW when operated on 1.8 V supply with SNR, SFDR and ENOB as 22.5 dB, 32.4 dBc and 3.8 bits while for 6 bit the SNR, SFDR and ENOB are 34.96 dB, 42 dBc and 5.56 bits respectively with 0.35 mW of power dissipation. The Walden FOM for proposed 4 bit and 6 bit ADC design are 0.21 pJ/conversion-step and 24.7 fJ/conversion-step respectively.