Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

Conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to netlists of RSFQ circuits considering reduction of the number of clocked gates including DFFs for path balancing. It utiliz...

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Veröffentlicht in:	IEEE transactions on applied superconductivity 2020-10, Vol.30 (7), p.1-1
Hauptverfasser:	Kito, Nobutaka, Takagi, Kazuyoshi, Takagi, Naofumi
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit design Circuit faults Clocks CMOS Conversion Delay time Delays design automation digital circuits Gates Integer programming Integrated circuit modeling Linear programming Logic circuits logic design Logic gates Multiplexing Pattern generation RSFQ circuits superconducting integrated cir-cuits Test pattern generators
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