Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

Conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to netlists of RSFQ circuits considering reduction of the number of clocked gates including DFFs for path balancing. It utilizes two kinds of special RSFQ gates for the reduction. One is a confluence buffer which can be utilized for realizing logic-OR. The other is a small resettable DFF which can be utilized as an NIMPLY gate with the tuning of the order of pulse arrivals. Detection methods of replaceable gates with those two kinds of gates are proposed. An ATPG tool is utilized for detecting replaceable OR gates to speed up the previously proposed detection method. To minimize the number of clocked gates considering cost of replacements, the selection problem of gates for replacements with those special RSFQ gates and assignment of a logic level for each gate are formulated as an instance of integer linear programming. The proposed conversion method has been evaluated with ISCAS85 circuits, a 32-bit ALU and a 64-bit ALU. Evaluation results show that the number of clocked gates and the latency in cycles of circuits are reduced about 10%. The delay time of the converted circuits has been estimated and reduction of delay overhead is discussed.