A Generic Methodology for Breakdown Voltage Optimization of Lateral Silicon‐On‐Insulator Power Devices

A generic optimization methodology is presented for the design of drift region in lateral silicon‐on‐insulator (SOI) power devices. The methodology targets a drift region design with a low on resistance and a high reverse blocking capability. 2D drift diffusion technology computer aided design (TCAD) simulations are used to arrive at the principles of operation. As the drift region is a critical component of any lateral power device, the simulation domain is isolated to a generic n‐doped Si drift region, with symmetric top and bottom oxide (SiO2) layers. A qualitative explanation based on charge sharing and the resulting electric field modulation is provided. The presence of oxide layers causes the drift region to be modulated such that it enables one to achieve a higher breakdown at a higher doping density. The main design parameters like drift doping, thickness, drift length, and oxide thickness are varied, and optimum values are identified for each. Finally, the extension of this optimization algorithm to other variants of lateral SOI devices is discussed. The objective of power device designers has always been to maximize reverse blocking voltage while minimizing on resistance. This work provides a generic methodology to optimize breakdown voltage of lateral silicon‐on‐insulator (SOI) power devices. The optimization algorithm is presented for key drift region parameters common to many design topologies. Technology computer aided design (TCAD) simulations provide key physical insight.