A high‐resolution all‐digital pulse‐width modulator architecture with a tunable delay element in CMOS

Summary A design for an all‐digital high‐resolution pulse‐width modulator (HRPWM) architecture is presented in this work. The architecture is based on a novel digitally controlled delay element that combines two different approaches, achieving a variable time interval up to 54 ps, and adjustable against process, voltage, and temperature (PVT) variations. The proposed system uses several delay elements with a counter‐based digital pulse‐width modulator (DPWM) in a hybrid configuration, which allows to obtain duty cycles with 18‐bit resolution without using a high‐frequency internal clock and maintaining a low power dissipation. The HRPWM was implemented in a standard low‐cost 130‐nm CMOS technology, together with a memory used to store the duty cycles, and a serial communication module. Post layout simulation results show good linearity between the control word and the duty cycle in all the range. The chip can be fine tuned to improve its performance using the calibration capabilities of the architecture. The analysis includes a comparison with another state‐of‐art HRPWMs showing the advantages of the proposed approach. In this paper, we present an all‐digital high‐resolution pulse‐width modulator (HRPWM) architecture based on a novel digitally controlled delay element, which achieves a variable time interval up to 54 ps and can be adjusted against process, voltage, and temperature variations. The HRPWM was developed in a standard 130‐nm CMOS technology and postlayout simulation results show good linearity between the control word and the duty cycle in all the range.