Orientation‐Controlled Selective‐Area Epitaxy of III–V Nanowires on (001) Silicon for Silicon Photonics
Monolithic integration of III–V nanowires on silicon platforms has been regarded as a promising building block for many on‐chip optoelectronic, nanophotonic, and electronic applications. Although great advances have been made from fundamental material engineering to realizing functional devices, one...
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Veröffentlicht in: | Advanced functional materials 2020-07, Vol.30 (30), p.n/a |
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Sprache: | eng |
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Zusammenfassung: | Monolithic integration of III–V nanowires on silicon platforms has been regarded as a promising building block for many on‐chip optoelectronic, nanophotonic, and electronic applications. Although great advances have been made from fundamental material engineering to realizing functional devices, one of the remaining challenges for on‐chip applications is that the growth direction of nanowires on Si(001) substrates is difficult to control. Here, catalyst‐free selective‐area epitaxy of nanowires on (001)‐oriented silicon‐on‐insulator (SOI) substrates with the nanowires aligned to desired directions is proposed and demonstrated. This is enabled by exposing {111} planes on (001) substrates using wet chemical etching, followed by growing nanowires on the exposed planes. The formation of nanowire array‐based bottom‐up photonic crystal cavities on SOI(001) and their coupling to silicon waveguides and grating couplers, which support the feasibility for on‐chip photonic applications are demonstrated. The proposed method of integrating position‐ and orientation‐controllable nanowires on Si(001) provides a new degree of freedom in combining functional and ultracompact III–V devices with mature silicon platforms.
Integration of III–V nanowires on silicon (001) platforms is demonstrated, with the ability to control the position and orientation of nanowires. Nanowire array‐based photonic crystal cavities are formed on silicon‐on‐insulator photonic platforms by this approach, substantiating that the proposed method could be utilized for combining functional and ultracompact III–V devices with mature silicon platforms. |
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ISSN: | 1616-301X 1616-3028 |
DOI: | 10.1002/adfm.202002220 |