A 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers

This paper presents a 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers. To reduce size overhead from the dual‐mode interfaces, we propose the termination circuit that shares 50‐Ω terminations and common‐mode capacitors while maintaining a perfectly matched l...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	Journal of the Society for Information Display 2020-06, Vol.28 (6), p.535-547
Hauptverfasser:	Kim, Tae‐Jin, Hwang, Jong‐Il, Lee, Sangkyu, Chun, Sengsub, Ryu, Seong‐Young, Lee, Soo‐Joo, Cho, Hyunwoo, Tak, Wonho, Kim, Yong‐Jae, Lee, Hoomin, Pae, Hansu, Lim, Hyun‐Wook, Lee, Jae‐Youl
Format:	Artikel
Sprache:	eng
Schlagworte:	balanced coding Circuits clock recovery clock‐embedded signaling CMOS deskew circuit display driver dual‐mode receiver host interface Load matching MIPI C‐PHY MIPI D‐PHY tri‐signaling
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!