FPGA Implementation of Homotopic Path Planning Method with Automatic Assignment of Repulsion Parameter
In recent times, autonomous robots have become more relevant, aiming not only to be an extension of mobility and human performance but also allowing them to independently solve specific problems such as finding free-collision paths within some defined environments. In order to achieve this, several...
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Veröffentlicht in: | Energies (Basel) 2020-05, Vol.13 (10), p.2623, Article 2623 |
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Sprache: | eng |
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Zusammenfassung: | In recent times, autonomous robots have become more relevant, aiming not only to be an extension of mobility and human performance but also allowing them to independently solve specific problems such as finding free-collision paths within some defined environments. In order to achieve this, several techniques have been developed, like action-reaction algorithms, sampling-based algorithms, and deterministic algorithms such as the Homotopy Path Planning Method (HPPM). This work presents, for the first time, a complete deterministic collision-free path planning scheme implemented in FPGA, which is mounted on a Scribbler 2 robot from Parallax. Then, an automatic algorithm of the repulsion parameter for the HPPM method is presented, using as a reference the minimum distance between the center of each obstacle with respect to the homotopic ideal path; furthermore, an algorithm is proposed for discriminating dead-end routes and collision risk trajectories, which allows us to obtain a feasible free-collision path that takes into account the robot dimensions. Besides, comparative performance tests have been carried out against other path-finding methods from the low degrees of freedom (low DoF) and sampling-based planners. Our proposal exhibits path calculation times which are 5 to 10 times faster on FPGA implementation, compared to the other methods and 10 to 100 times faster on PC implementation also compared to the rest. Similar results are obtained with regards to memory consumption, namely 20 to 200 times lower on FPGA implementation and 10 to 100 times lower on PC implementation. |
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ISSN: | 1996-1073 1996-1073 |
DOI: | 10.3390/en13102623 |