Efficient multiquality super‐resolution using a deep convolutional neural network for an FPGA implementation

We propose an efficient deep convolutional neural network for a super‐resolution which is capable of multiple‐quality input, by analyzing the input quality and choosing appropriate features automatically. To implement the network in an FPGA and an ASIC, we employ a network trimming technique to compress the neural network. Efficient deep convolutional neural network for a super‐resolution which is capable of multiple‐quality input. First we train Single Quality‐SR (SQSR) for each quality and optimize with network trimming. Then we insert selection layers between concatenated SQSRs and train them for analyzing the input quality and choosing appropriate deconvolution features automatically.